
TM 9-6625-474-14&P-3
The Gate Generator circuit also produces the Latch
Trigger and a complementary Measurement Gate going to
the Measurement Cycle Timing circuit on schematic 5.
The operation of the Latch Trigger circuit is the same for
all modes of operation that requires a Measurement Gate
and will be described only once.
The generation of the Latch Trigger signal starts
whenever pin 3 of U1410A goes high at reset (clear) for the
Gate Generator. At reset, pin 13 of U1330D goes high and
pin 15 goes low. This low is transmitted without inversion
through buffer U1122D. Therefore, the Latch Trigger
signal on pin 14 of U1122D goes low whenever the Gate
Generator is cleared.
As soon as a positive clock edge occurs on pin 6 of
U1410A, pin 3 goes low and pin 15 of U1330D goes
momentarily high. However, pin 15 of U1410B is con-
nected to pin 12 of U1330D and as soon as that signal goes
high, pin 15 of U1330D goes low again. This action causes
a momentary positive pulse immediately after first clock-
ing the Gate Generator. This small pulse does not affect
the operation of the instrument.
At the end of the Measurement Gate, pin 15 of U1410B
goes low again. When this happens there will be a low on
pin 12 and pin 13 of U1330D, causing a low to high
transition on its output. It is the second low to high
transition at the end of the Measurement Gate interval that
produces the Latch Trigger and affects the Measurement
Cycle Timing circuit.
PERIOD B (Variable Clock). For this mode, a Measure-
ment Gate is generated from the Channel B input signal
and the Time Base is counted (divided down or not). Since
this is a single period measurement, the Time Base signal
(10 MHz) is again routed to the
N Circuit via U1320C.
During the single period the instrument counts 10 MHz, or
1 MHz, or 100 kHz, etc. The N output again appears at
the emitters of Q1330and Q1320. Forthis mode itis Q1330
that is turned on in a saturated mode, allowing the divided
d o w n T i m e B a s e s i g n a l t o p a s s o n t o t h e D e c a d e
Accumulators.
The Measurement Gate is generated from the CH B
signal with U1420A enabled on pin 4 (low). The single
period signal from CH B passes on through U1421C, then
on through Q1321 because its base is low.
On the first rising edge of the single period, the start of
the Measurement Gate
IS
generated exactly the same as
previously discussed under the FREQUENCY A mode of
operation. On the next rising edge of thesingle period, the
Measurement Gate is stopped with pin 14 of U1410B high
and pin 15 low.
The gate signal generated on pin 14 of U1410B is again
routed through and inverted by both U1330B and U1220C.
PERIOD B (Average). For this mode the Time Base
signal is passed through U1330A directly to the Decade
Accumulators. The Channel B signal is routed to the
N
Circuit via U1420A, U1421C, and Q1331 (base is low). The
divided down Channel B signal returns via Q1320 to clock
the Gate Generator.
The first edge to clock the Gate Generator is the first
edge of signal period. That edge is divided down by the
N Circuit to generate the second edge through Q1320
and terminate the Measurement Gate. The instrument is
averaging over 10” number of Channel B signal periods to
generate the Measurement Gate.
WIDTH B (Variable Clock). This mode of operation is
exactly like PERIOD B (Variable Clock), except that the
instrument counts the Time Base signal (divided by N, or
not) during the positive portion or negative portion of the
input signal period to Channel B. Whether the positive
pulse width or negative pulse width is measured depends
on the setting of the SLOPE switch, S1020. The Time Base
signal passes through U1320C, out to the
N Circuit,
b a c k i n t h r o u g h Q 1 3 3 0 a n d o n t o t h e D e c a d e A c -
cumulators.
The exclusive-OR gate, U1421C, along with NOR gate,
U1430B, is used to generate a single width measurement.
The Channel B signal appears on pin 14 of U1421C. Pin 15
is low at this time, causing U1421C to operate as a non-
inverting buffer. When pin 14 goes from low to high, the
output, pin 13, also goes from low to high. The positive
transition is passed through Q1321 (base is low) and
clocks the Gate Generator on the first rising edge of the
Channel B input, starting the Measurement Gate (pin 14 of
U1410B goes low).
Pin 7 of U1430B is at a logic low for this mode. When the
Measurement Gate starts, pin 6 goes low and sets a high
logic level on pin 15 of U1421C. During the Measurement
Gate interval, U1421 C operates as an inverter. The next
falling edge from Channel B (end of the positive pulse) will
cause another positive edge to clock the Gate Generator
and terminate the Measurement Gate. The Measurement
Gate is again routed through U1330B and U1220C,
enabling the Decade Accumulators to count the Time
Base during the positive pulse width.
WIDTH B (Average). This mode of operation is similar
to Period B (Average), except that NOR gates U1430C and
U1430A are involved in the process. With U1430C enabled
on pin 10, the Channel B pulse width passes through
U1430C to pin 4 of U1430A. The Channel B signal also
Содержание DC503a
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Страница 16: ...DC 503A DC 503A Universal Counter Timer REV A FEB 1981 XIV ...
Страница 27: ...Fig 2 2 Controls and connectors Operating Instructions DC 503A 2977 fli English 2 3 ...
Страница 39: ...Fig 2 2 Commandes et prises Instructions d utilisation DC 503A French 2 3 ...
Страница 51: ...Abb 2 2 Bedienungselemente and Anschliisse Bedienungsanleitung DC 503A German 2 3 ...
Страница 63: ...Fig 2 2 Controls and connectors Operating Instructions DC 503A 2971 01 Japanese 2 3 ...
Страница 125: ...Fig 8 2 Auxiliary Board A12 Assy ADJUSTMENT LOCA 2971 1 6 ...
Страница 169: ...SEE END OF MPL FOR WIRE ASSEMBLIES O1 0 pG C 0 DC 503A ...
Страница 186: ...0 2 TM 9 6625 474 14 P 3 Fig 0 1 DC 503A Universal Counter Timer ...
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Страница 197: ...2 3 TM 9 6625 474 14 P 3 Fig 2 2 Controls and connectors ...
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Страница 219: ...4 2 TM 9 6625 474 14 P 3 Table 4 1 LIST OF TEST EQUIPMENT REQUIREMENTS ...
Страница 240: ...5 7 TM 9 6625 474 14 P 3 Fig 5 9 Rear interface connector assignments ...
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Страница 259: ...8 9 8 10 blank TM 9 6625 474 14 P 3 PARTS LOCATION GRID Table 8 1 COMPONENT REFERENCE CHART See Fig 8 3 ...
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Страница 275: ...8 41 8 42 blank TM 9 6625 474 14 P 3 DC 503A Table 8 9 COMPONENT REFERENCE CHART See Fig 8 3 ...
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Страница 291: ...D 1 TM 9 6625 474 14 P 3 APPENDIX D MANUAL CHANGE INFORMATION ...
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Страница 299: ...THE METRIC SYSTEM AND EQUIVALENTS ...
Страница 300: ...PIN 056816 000 ...