Tektronix DC 502, Инструкция по эксплуатации

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Theory of Operation — DC 502
NOR gate U230C goes HI, producing the CLEAR and
CLEAR control signals. The next HI-to-LO transition from
the 1-MHz clock (T2) toggles U222A, causing its Q output
to go HI and its Q to go LO. With a LO applied to one of its
inputs, U230A rev erts to its original condition, terminating
the CLEAR and CLEAR pulses. The DDU's then start
counting from their 0999999 reset condition.
At the end of a 10-microsecond delay (time for the
DDU's to count the first digit, plus a propagation delay), a
negative transition from the DDU's via the MEASURE­
MENT INTERVAL switch toggles U220B. This corresponds
to T3 in Fig. 2-1. U220B's Q output goes HI and its Q
output goes LO. The next negative transition from the
1-MHz clock (T4) toggles U222B, causing its Q output to
go HI (GATE open) and its Q output to go LO (supplying
current to the front-panel GATE indicator LED, DS225).
The GATE signal is also applied to the base of Q230,
saturating the transistor and preventing C235 from
charging.
The GATE remains open (HI) for the time duration
selected by the MEASUREMENT INTERVAL switch. At
the end of this time, which corresponds to T5 in Fig. 2-1,
another negative transition from the_DDU's toggles U220B.
U220B's Q output goes LO and its Q output goes HI. The
next negative transition from the 1-MHz clock (T6) toggles
U222B, causing its Q_output to go LO, closing the GATE.
Simultaneously, the Q output goes HI, removing current
from the GATE indicator LED.
When the GATE output goes LO,_the negative transition
toggles U220A, switching Q LO and Q HI. Now NAND gate
U230D has two HI inputs, placing a LO at the input of OR
gate U230B and activating the LATCH control signal (HI
state). One microsecond later (T7), a negative edge from
the 1-MHz clock toggles U222A, switching its outputs and
placing a LO on the input of NAND gate U230D. U230D
reverts to its original condition, terminating the LATCH
signal.
The display time begins when the GATE signal ends
(T6). When Q230 turns off, C235 begins to charge through
R232-R235 toward the Vcc supply. R235, DISPLAY
TIME, provides an adjustable time constant to vary the
display time from about 0.1 second to about 10 seconds.
When the DISPLAY TIME control is fully clockwise
(HOLD detent position), S235 opens, and C235 stops
charging. When S235 is closed and C235 charges
sufficiently to bring Q238 to its firing potential (T1, the
display time ends and the next GATE-opening sequence
begins.
Manual Gate
The manual mode of operation is selected by placing the
MEASUREMENT INTERVAL switch in the MANUAL
position. The switch closure to ground (cam 5 of the
switch) places a LO on the set inputs of U220B and
U222A, and a LO on the clear input of U220A. This forces
the Q outputs of U222A and U220B HI, and the Q output
of U220A LO. With both inputs of U230D held HI, the
LATCH output is held HI, allowing the counter to update
the display continuously. The GATE is opened when the
front-panel START button is pushed in, opening S210 and
applying a HI to the clear input of U222B. As before, the
GATE-open condition is HI at the Q output of U222B. The
GATE is then closed when S210 is set to STOP (button
out). To reset the counters in the manual mode, the RESET
button must be pushed to activate to CLEAR, CLEAR and
RESET control signals.
COUNTER
Decade Counter Units (DCU's)
The 10° through 106 DCU's are seven cascaded
divide-by-ten counters. The first decade counter is made up
of four
individual J-K flip-flops to accept the high-speed
decade input (up to 100 MHz), and each subsequent DCU is
a single IC. U165A, U165B, U167, and U169 comprise the
first (10°) decade counter, and U235 through U240 make
up the remaining six DCU's.
When the J and K inputs of U165B are HI (GATE open),
the counter is enabled. The input signal is applied to the
toggle input of U165B. On every tenth clock input counted
by the first decade counter, the output of U169 goes LO,
providing a carry signal which becomes the clock input for
the second decade counter. Each subsequent decade divides
CIRCUITS
by ten in a similar manner. Four BCD output lines are
connected from each DCU to its associated storage-register
latch. When the CLEAR (HI) and CLEAR (LO) signals are
activated, all of the decade counters are reset to the
zero-count state.
Storage Register
The seven IC latches (U250 through U256) comprise a
storage register which stores the corresponding decade
counter BCD output. The BCD output is applied to the
data inputs at pins 1, 5, 7, and 3 (2°, 21, 22, and 23 bits
respectively). The LATCH pulse is applied to the data-
strobe input at pin 2 of each latch immediately upon
closure of the GATE or when the MEASUREMENT
INTERVAL switch is placed in the MANUAL position, as
2-3