Tektronix 7623, Инструкция по эксплуатации

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Circuit Description— 7623/R7623 Service
Fig. 3-6. (A) Logic diagram for Vertical Chopped Blanking stage, (B) Table of input/output combinations for Vertical Chopped Blanking stage.
pulse produced by the Clock Generator stage provides the
timing signal for this stage. A logic diagram of the Chop
Counter, identifying the inputs and outputs, is shown in
Fig. 3-7.
The Chop Counter stage consists of integrated circuit
U123, a dual D-type flip-flop with direct-set, direct-clear
inputs
(see Table 3-1 for operation of D-type flip-flop). As
connected in this circuit, these D-type flip-flops operate as
triggered (toggle) flip-flops.
The two-megahertz clock pulses from the Clock Gen­
erator stage are connected to the trigger (T) input of
U123B. As connected, U123B changes output states with
each positive-going Clock pulse, and the signal at its "1"
output is a square wave which switches between the HI and
LO levels at a one-megahertz rate. This signal is connected
to the Vertical Mode Control stage to provide the Vertical
Mainframe Chop Signal. It is also connected to the trigger
input of U123A. U123A also changes output states with
each positive-going pulse at its trigger input to produce a
500 kilohertz square wave at its "1" output. The output
from U123A provides the Vertical Plug-In Chop Signal to
3-12