Tektronix 7623, Инструкция по эксплуатации

Страница: 95 / 266

Circuit Description-7623/R7623 Service
STORAGE CIRCUITRY
The Cathode-Ray tube of the 7623 is an image transfer
storage tube. In the FAST mode, the display is first stored
on a high speed mesh (target). The information is then
transferred to the direct viewing screen. The FAST mode of
storage is capable of writing rates greater than
50 divisions/µs for long periods of time. The store circuitry
for the high speed mesh is adjusted for fastest writing
speed; the direct viewing screen circuitry is adjusted for
longest retention and best display.
The storage circuitry is located on two boards (Storage
Logic and Storage Output). The Storage Logic board has
the switch and diode matrix and develops the timing pulses
needed for the different storage modes. The calibrator
signal voltage divider network and the AC to DC jumper are
also located on the storage logic board. The Storage Output
board provides the CRT with the required voltage levels for
proper storage operation. Most of the output circuits are
high voltage gated operational amplifiers.
The first output from pin 11 section D resets the
G
l
flip-flop, stopping the clock pulses from the ripple counter,
and resets the sweep lockout flip-flop so that a sweep can
occur.
Sweep Lockout Circuit
The holdoff gate signal from the horizontal time base
plug-in unit is connected to a monstable multivibrator to
generate QT and ÖT pulses. The pulses are developed after
the sweep, and are about 100 ms long. The GT pulse resets
the sweep lockout flip-flop so that no sweep can occur until
an erase cycle has been generated in the Fast Storage mode
only. In the Non-Store mode, the sweep lockout function is
prevented from locking out any sweeps. See Fig. 3-40, basic
block diagram, for storage timing circuits. In the Save
mode, the sweep lockout is on so that no sweeps can occur.
In the Integ mode, when the INTEG button is pressed, the
sweep lockout is off to provide a repetitive sweep.
The switch and diode matrix provides several different
command output lines per switch function. See Table 3-5
for the list of outputs for each switch position. A ground
closure by the switch forward-biases several diodes at
different output lines. In this manner, one switch can con­
trol several output lines.
Erase and Timing Circuits
Manual erase is accomplished by pressing the MAN
ERASE button or grounding the remote erase connector on
the rear panel. This grounds the junction of resistor R177O,
R1767, and R1771. Voltage divider R1767-R1761 provides
programmable unijunction Q1777 with a gate voltage
slightly lower than the anode voltage. This causes Q1774 to
become forward biased, and capacitor C1773 is allowed to
discharge through Q1774. This produces a positive pulse at
the base of Q1777, which inverts the pulse and triggers RS
flip flop U1780A and U1780C for a C|_ pulse and a Qß
pulse. When
C
l is high, transistor Q1769 turns on to
prevent C1773 from recharging and discharging. When
G
l
'
s
at a high level, transistor Q1784 is turned off, allowing the
timing capacitor C1785 to charge through resistor R1785.
When the anode voltage level increases to about the same
voltage level as the gate voltage level, the programmable
unijunction transistor will turn on, producing a positive
pulse. Programmable unijunction transistor Q1788 provides
the clock pulses for U1790, a high-speed ripple-through
counter. The counter develops the sequential pulses used to
set and reset the RS flip-flops. See Fig. 3-38 for basic block
diagram storage circuit. See Fig. 3-39 for output pulses.
Auto Erase Circuit
The auto erase circuit uses a programmable unijunction
transistor for a variable pulse generator. The setting of the
AUTO VIEW TIME determines the charge rate of timing
capacitor C1749. When the anode voltage level increases to
where the gate voltage level turns on the programmable
unijunction transistor (p.u.t.), a positive pulse is generated.
This signal is connected to the base of transistor Qi 759,
turning it on. When transistor Q1759 is turned on, the gate
voltage level of Q1774 will decrease and start an erase and
timing cycle. The sweep lockout flip-flop controls one
input to the auto erase flip-flop, preventing an auto erase
cycle from occurring before the sweep has occurred. If pin
3
of U1745A (the auto erase flip-flop) is high (one state),
transistor Q1747 is turned on, and the timing capacitor
cannot charge. When the sweep gate flip-flop has been reset
by a sweep, pulse QT resets the auto erase flip-flop, so that
pin 3 of U1745A is low and turns transistor Q1747 off.
This allows the timing capacitor to charge, which starts an
erase
cycle and timing pulses.
When the VAR PERSIST, FAST or BI-STABLE buttons
are pressed, an erase cycle should be generated. Transistor
Q1757 is turned on by the discharging of capacitors C1669,
C1678,
or C1693, depending on the switch buttons pressed.
When transistor Q1757 is turned on, transistor Q1759 is
also turned on, lowering the gate voltage level on Q1774 to
where it can turn on, initiating an erase cycle. See Fig. 3-40
basic block diagram for the storage timing circuit.
3 49