Tektronix 2236, Инструкция по эксплуатации

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Theory of Operation— 2236 Service
B Trigger Level Comparator (SN B014886 & UP)
The B Trigger Level Comparator is composed of transis­
tor array U605, U625, Q619, and Q620. This circuit deter­
mines both the trigger level and slope at which the B
triggering signal is produced. It functions in the same man­
ner as the A Trigger Level Comparator with the exclusion of
the TV Trigger and Trigger View circuitry. See the “A Trig­
ger Level Comparator” section for a description of the circuit
operation. Buffering of the noninverting output of U625B is
provided by U625A, and Q630 and Q631 level shift the sig­
nals to TTL Levels. The inverting output of U625A also pro­
duces the B Trigger signal used by the CTM circuitry. The
circuit output at the collector of Q630 supplies trigger sig­
nals to clock U670A.
B Trigger Level Comparator
(SN B014885 & BELOW)
The B Trigger Level Comparator is composed of transis­
tor array U605, U625C, Q619, and Q620. This circuit deter­
mines both the trigger level and slope at which the B
triggering signal is produced. It functions in the same man­
ner as the A Trigger Level Comparator with the exclusion of
the TV Trigger and Trigger View circuitry. See the “A Trig­
ger Level Comparator” section for a description of the circuit
operation. Buffering of the inverting and noninverting out­
puts of U625D is provided by U625A and U625B, and Q630
and Q631 level shift the signals to TTL levels. The output of
U625A also produces the B Trig signal used by the CTM
circuitry. The circuit output at the collector of Q630 supplies
trigger signals to clock U670A.
Runs After Delay
The Runs After Delay circuit allows the B Sweep Logic to
generate a B Sweep independently of any B Trigger signals.
In the Runs After Delay mode, B TRIGGER LEVEL control
R602 is rotated fully clockwise. This biases off Q637 and
places a LO on the collector. Inverter U660D will then have
a HI output with resistor R640 providing positive feedback.
The output of U660A will therefore be LO and U670A will be
held set with the Q output LO.
If the B TRIGGER LEVEL control is not fully clockwise,
Q637 is biased on and the B Sweep is in the triggered
mode. The output of U660D will be LO, the output of U660A
will be HI, and U670A will no longer be held set.
Operation of the B Sweep Logic circuitry under both of
these conditions is described in the “B Sweep Logic” dis­
cussion. The output signal of U660D is applied to the CTM
Intensified Zone Controller circuitry and serves as an input
to U1603.
B Delay Time Position Comparator
The B Delay Time Position Comparator circuit compares
the amplitude of the A Sweep sawtooth output voltage to
the dc voltage level set by B DELAY TIME POSITION
potentiometer R9644. The output of the comparator is used
to initiate a B Sweep and to control the B Z-Axis Logic
circuit switching.
The inputs to the comparator, U655, are the Delay signal
from the Analog Section of the Delay/Delta Time Controller
circuit and the A Sweep voltage from the divider network
composed of R651, R652, and R653. Input voltage ranges
to the comparator are determined by VR645 and R646 for
the noninverting input and by R652 for the inverting input.
Delay Start potentiometer R646 is adjusted in conjunction
with potentiometer R652 to set the B DELAY TIME POSI­
TION dial calibration.
The output of the comparator is enabled or disabled by
the strobe signal connected to pin 6. When the A Only sig­
nal is HI, the comparator is enabled. When A Only is LO,
the output of the comparator is a high impedance and there­
fore a HI is present on pin 9 of U680C.
B Sweep Logic
The B Sweep Logic circuitry utilizes signals from the as­
sociated B Sweep circuitry to generate control signals for
both the B Miller Sweep and the B Z-Axis Switching Logic
circuits.
_ In the Runs After Delay mode, U660A places a LO on the
S input of U670A. During the previous holdoff period,
U680D pin 13 strobed LO. The output of the flip flop com­
posed of U680C and U680D went H ljin d the output of
U660F went LO. With both the S and R inputs of U670A
LO, the Q output is HI to bias on Q709 and prevent the B
Miller Sweep from running. Once the A Sweep voltage at
U655 pin 3 exceeds the voltage at pin 2, the comparator
output will go LO. The flip flop composed of U680C and
U680D will change output states_and cause the R input of
U670A to be HI. The LO on the S input will then cause the
Q output of U670A to go LO. The Delay End signal at the
output of U665A will go LO to indicate to the CTM circuitry
that the B Sweep has started. Transistor Q709 will shut off
and the B Miller Sweep Generator will produce a linear
ramp. If the ramp voltage reaches about 12 V, sweep-end
comparator Q643 will turn on and cause the output of
U665D to go HI. The B Miller Sweep Generator will continue
to run, but the trace will be blanked because the ¥ Gate line
is HI which reverse biases CR817. Once the ramp is at ap­
proximately 13 V, VR712 will conduct and prevent the volt­
age from increasing further.
The B Sweep Generator will be reset for another sweep
by one of two means. If the A Sweep doesn’t end before the
B Sweep, the Generator will not be reset until the Alt Sync
line goes from HI to_LO to change the U680C-U680D flip-flip
output states. The R input of U670A will then be LO, caus­
ing the Q output to be HI and reset the Generator. Depend­
ing on the settings of the A and B SEC/DIV switches, the A
Sweep may end before the B Sweep. If this occurs, the Alt
Sync line will go LO at the end of the A Sweep and cause an
immediate resetting of the Generator. In either case, a new
sweep will be initiated the next time the A Sweep voltage at
U655 pin 3 exceeds the voltage at pin 2.
When not in the Runs After Delay mode, the output of
U660A is HI and U670A has a HI on both the S and D
inputs. The circuitry connected to the R input of U670A
REV MAR 1985
3-13