Tektronix 2215A, Инструкция по эксплуатации

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Theory of Operation— 2215A Service
Input Coupling
The signal applied to the CH 1 OR X input connector can
be ac coupled, dc coupled, or disconnected from the input of
the High-Impedance Input Attenuator circuit. Signals applied
to the CH 1 OR X input connector are routed through resis­
tor R9100 to Input Coupling switch S I. When SI is set for
dc coupling, the Channel 1 signal is applied directly to the
input of the High-Impedance Attenuator stage. When ac
coupled, the input signal passes through dc-blocking capac­
itor C2. The blocking capacitor prevents the dc component
of the input signal from being applied to the Attenuator cir­
cuit. When switched into the signal path, attenuators ATI
and AT2 attenuate the input signal by factors of 100 and 10
respectively. When SI is set to GND, the direct signal path
is opened and the input of the Buffer Amplifier is connected
to ground. This provides a ground reference without the
need to disconnect the applied signal from the input connec­
tor. The coupling capacitor precharges through R4 to pre­
vent large trace shifts when switching from GND to AC.
Buffer Am plifier and Gain Switching Network
The Buffer Amplifier presents a high-impedance, low-ca­
pacitance load to the signal from the High-Impedance Atten­
uator and a low output impedance to the Gain Switching
Network. A dual-path amplifier is used to combine high-dc
stability with high-speed performance.
In the slow path, the input signal is applied to both the
gate of source-follower Q13 and the inverting input of U10
through the divide-by-two network composed of R3 and R5.
Transistor Q13 and emitter-follower Q18 isolate the input
signal from the loading of the Gain Switching Network. The
divider network at the output of the Amplifier (R46, R47, and
R48) is connected to the other input of U10. Amplifier U10
compares the two divider voltages and changes the conduc­
tion level of current-source transistor Q15 to correct for any
error at the source of Q13. Capacitor C l 0 limits the band­
width of U10 so that the slow path responds only to fre­
quencies below 100 kHz.
In the fast path, input signals are coupled through R6,
C6, Q13, and Q18 to the circuit output. By adjusting R47,
the gain in both paths is matched. Input offset voltage com­
pensation for U10 is provided by RIO to eliminate trace
shifts when switching between Volts/Div settings.
The Gain Switching Network divides down the Buffer
Amplifier output signal for application to the Paraphase Am­
plifier and has an output impedance of 75 Q for all Volts/Div
switch settings. The particular Volts/Div switch setting will
determine which contacts of SI 0 are closed and therefore
whether the Paraphase Amplifier will receive a — 1, — 2,
-5- 4, or -f- 10 signal.
Paraphase Am plifier
The Paraphase Amplifier converts the single-ended sig­
nal from the Gain Switching Network into a differential sig­
nal for application to the Vertical Preamplifier. Included in
the circuitry is switching that provides extra gain for the
2 mV position of the VOLTS/DIV switch, adjustments for
amplifier dc balance, and circuitry for the Variable Volts/Div
function. Additionally, the Channel 2 Paraphase Amplifier
contains circuitry to invert the Channel 2 display.
The signal from the Gain Switching Network is applied to
the base of one transistor in U30. The other input transistor
is biased by the divider network composed of R30, R31, and
R33 to a level that will produce a null between the outputs of
U30 (no trace shift on the crt screen) when the VOLTS/DIV
control is switched between 5 mV and 2 mV. Emitter current
for the two input transistors is supplied by R21, R22, R23,
and R25, with R29 serving as the gain-setting resistor be­
tween the two emitters. In the 2 mV position, amplifier gain
is increased by closing contact 15 of SI 0 to shunt R29 with
R26.
The collector current through the two input transistors
serves as emitter current for the two differential output tran­
sistor pairs. Base-bias voltages for the two pairs are derived
from the divider network composed of R39, R41, R42, and
R43. Monolithic 1C U30 has matched transistor characteris­
tics, so the ratio of currents in the two diodes connected to
pin 11 determines the current ratios in the output transistor
pairs. As VOLTS/DIV Variable potentiometer R43 is rotated
from the calibrated to uncalibrated position, the conduction
level of the transistors connected to R35 will increase. Since
the transistor pair outputs are cross-wired, this increased
conduction will subtract from the signal produced by the
transistors connected to R38 and the overall gain of the
Amplifier will decrease. Potentiometer R25 adjusts the bal­
ance of the Amplifier so there is minimal dc trace shift as the
VOLTS/DIV Variable control is rotated.
Incorporated in the Channel 2 Paraphase Amplifier is cir­
cuitry to invert the polarity of the Channel 2 signal. When
INVERT switch S90 is out, the transistor pairs in U80 are
biased as they are in U30 and there is no trace inversion.
For the IN position of S90, connections to the bases of the
output transistor pairs are reversed to produce an inverted
Channel 2 trace. Potentiometer R75 is adjusted so that
there is minimal dc trace shift as the INVERT button is
changed between the IN and OUT positions.
VERTICAL PREAMPLIFIERS
The Vertical Preamplifier, shown on Diagram 2, utilizes
differential signal current from the Paraphase Amplifier to
3-4