TechNexion PICO-IMX6, Руководство по оборудованию

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PICO-IMX6 REV. A1. HARDWARE MANUAL
– VER 1.01 – JAN 28 2016
Page 17 of 64
2.1.1. i.MX6 Memory Interfaces

The memory system consists of the following components:
o
Level 1 Cache
—32 KB Instruction, 32 KB Data cache per core
o
Level 2 Cache
—Unified instruction and data (1 MByte)

On-Chip Memory:
o
Boot ROM, including HAB (96 KB)
o
Internal multimedia / shared, fast access RAM (OCRAM, 256 KB)
o
Secure/non-secure RAM (16 KB)

External memory interfaces:
o
16-bit, 32-bit, and 64-bit DDR3-1066 and LV-DDR3-1066
o
8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
o
BA-NAND, PBA-NAND, LBA-
NAND, OneNAND™ and others. BCH ECC up to 32 bit.
2.1.2. i.MX6 DMA Engine
The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by off-
loading the various cores in dynamic data routing. It has the following features:

Powered by a 16-bit Instruction-Set micro-RISC engine

Multi-channel DMA supporting up to 32 time-division multiplexed DMA channels

48 events with total flexibility to trigger any combination of channels

Memory accesses including linear, FIFO, and 2D addressing

Shared peripherals between ARM and SDMA

Very fast Context-Switching with 2-level priority based preemptive multi-tasking

DMA units with auto-flush and prefetch capability

Flexible address management for DMA transfers (increment, decrement, and no address
changes on source and destination address)

DMA ports can handle unit-directional and bi-directional flows (copy mode)

Up to 8-word buffer for configurable burst transfers

Support of byte-swapping and CRC calculations

Library of Scripts and API is available