PICO-IMX6 REV. A1. HARDWARE MANUAL
– VER 1.01 – JAN 28 2016
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2.2. Memory
The PICO-IMX6 integrates Double Data Rate III (DDR3) Synchronous DRAM in a single (32 bit) channel
configuration.
The following memory chips have been validated and tested on the PICO-IMX6 Compute Module:
2.2.1 SKHynix
SKHynix CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory
applications which requires large memory density and high bandwidth. SKHynix DDR3 SDRAMs offer
fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses
and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes
and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are
internally pipelined and 8-bit prefetched to achieve very high bandwidth.
SK Hynix memory features:
VDD=VDDQ=1.5V +/- 0.075V
Fully differential clock inputs (CK, CK) operation
Differential Data Strobe (DQS, DQS)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM masks write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
Programmable CAS latency 5, 6, 7, 8, 9, 10 and 11, 13 supported
Programmable additive latency 0, CL-1, and CL-2 supported
Programmable CAS Write latency (CWL) = 5, 6, 7, 8
Programmable burst length 4/8 with both nibble sequential and interleave mode
BL switch on the fly
8banks
Average Refresh Cycle (Tcase of 0o C~ 95 o C)
-
7.8 μs at 0 o C ~ 85 o C
-
3.9 μs at 85 o C ~ 95 o C
• Auto Self Refresh supported
JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA (x16)
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported
8 bit pre-fetch
More information can be retrieved from SKHynix:
Part number:
H5TQ2G63FFR-PBC preferred part 2Gbit
H5TQ2G63DFR-H9C backup part 2Gbit
H5TQ4G63FFR-PBC preferred part 4Gbit
H5TQ4G63DFR-H9C backup part 4Gbit
Содержание PICO-IMX6
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