As shown in the diagram above, the RZ6 architecture consists of three functional blocks:
Bus Related Delays
A standard two sample delay is associated with the zHop. However, these delays are managed
for the user in Synapse software.
Functional Signal Flow Diagrams
The following diagrams illustrate how analog signals for channels A and B
fl
ow through the
RZ6 and its modules. For more information on analog input and output see
The DSPs
Each DSP in the DSP Block is connected to a local interface to the three data buses: two
buses that connect each DSP to the other functional blocks and one that handles data
transfer between the DSPs. Each standard DSP is connected to 64 MB SDRAM and each core
in a QZDSP is connected to 256 MB DDR2. This architecture facilitates fast DSP-to-off-chip
data handling.
Because each DSP has its own associated memory, access is very fast and e
ffi
cient. However,
large and complex circuits should be designed to balance memory needs (such as data
buffers and
fi
lter coe
ffi
cients) across processors.
The maximum number of circuit components for each RZ5D standard RZDSP is 768 and 1000
for each QZDSP core.
The zBus Interface
The zBus interface provides a connection to the PC. Data and host PC control commands are
transferred to and from the DSP Block through the zBus interface bus, allowing for large high-
speed data reads and writes without interfering with other system processing.
The I/O Interface
The I/O interface serves as a connection to outside signal sources or output devices. It is
used to input data from the preampli
fi
er inputs and digital and analog channels. The I/O
interface bus provides a direct connection to each DSP.
RZ6 Multi I/O Processor | 7