5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Place all 1nF capacitors as close to package pins as possible.
PGND1 SHOULD NOT BE DIRECTLY
CONNECTOR TO PGND2 .they should
individely connected
Use tantalum or other high-frequency caps in all locations.
PDP42U3H
1
TMDS TRANSMITTER
20
21
Monday, June 14, 2004
Title
Size
Document Number
Rev
Date:
Sheet
of
FR_OUT4
DVI_TX2-
FR_OUT1
FB_OUT6
FG_OUT2
FB_OUT4
FG_OUT1
FG_OUT4
FPDE
FSHFCLK
FG_OUT5
FR_OUT2
FR_OUT0
FB_OUT1
FB_OUT0
FR_OUT7
FG_OUT3
FHSYNC
DVI_TX1-
FB_OUT7
FB_OUT2
FR_OUT5
FR_OUT3
FB_OUT3
FG_OUT7
FG_OUT6
DVI_TX0-
FG_OUT0
FB_OUT5
FR_OUT6
FVSYNC
DVI_TXC-
DVI_TX2-
DVI_TXC-
SCLK
DVI_TX1-
DVI_TX0-
SDATA
SLE
FVS
6,21
FPHS
6,21
FR_OUT[0..7]
6
FPDE
6,21
FB_OUT[0..7]
6
FPCLK
6,21
FG_OUT[0..7]
6
SCLK
10,21
SDATA
10,21
SLE
7,21
GND
PGND5
+3.3V
AVCC_3
PGND5
GND
GND
GND
L3.3V
GND
GND
GND
GND
GND
L3.3V
AVCC_3
GND
GND
GND
L3.3V
GND
+3.3V
PGND5
GND
L3.3V
GND
C307
0.1uF
C303
1nF
SiI 164
U28
36
37
38
39
40
41
42
43
44
45
46
47
50
51
52
53
54
55
58
59
60
61
62
63
4
5
2
57
6
7
8
21
22
24
25
27
28
30
31
19
23
29
20
26
32
18
49
17
48
1
12
33
64
35
11
13
10
34
15
14
9
3
16
56
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
HSYNC/SYNCI
VSYNC
DE
IDCK+
DK3
DK2
DK1
TXC-
TXC+
TX0-
TX0+
TX1-
TX1+
TX2-
TX2+
EXT_RES
AVCC
AVCC
AGND
AGND
AGND
PVCC
PVCC
PGND
PGND
VCC
VCC
VCC
GND
DKEN
MSEN/SOUT
ISEL/RST#
PD
RESERVED
BSEL/SCL
DSEL/SDA
EDGE/CHG
VREF
GND
IDCK-
R213
100
C309
0.1uF
R223
33K
C304
0.1uF
C320
1nF
C308
1nF
R219
100
FB39
R222
47
C310
10uF
R214
510 1%
R221
100
C318
1nF
R298
100
C311
1nF
R220
100
R217
100
C317
0.1uF
C312
0.1uF
C305
10uF
C316
10uF
JH2
HEADER 25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FB38
C319
0.1uF
R318
NC
C321
0.1uF
R218
100
C313
10uF
FB37
C315
0.1uF
C314
1nF
R299
4.7k
R216
100
C306
1nF
FB36
43
