5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
DVI INPUT
SDTV/HDTV
INPUT
VGA INPUT
PDP42U3 DIGITAL BOARD SCHEMATIC(FLI2300)
FRONT PANEL CONTROL BOARD
POWER BOARD
analog
board
interface
SERIAL PORT
(D-SUB9)
(D-SUB15)
(DVI-25)
(RCA*3)
SiI164
JAGASM
SiI161
FLI2310
AD9883A
80C32
89C2051
PI5V330
TB1274AF
TC90A69
PI5V330
4052
EL8300
prep.
THC63LVDS83
PDP42U3 don't use it.
PDP4226H should be
use it.
TCL MULTIMEDIA R&D. -- YangHong
1.0
PDP42
U3
H
/26H
DIGITAL BOARD(JAGASM)
Custom
1
1
Friday, February 20, 2004
Title
Size
Document Number
Rev
Date:
Sheet
of
OSC_13.5MHZ
<Value>
CLK
A18(FOR 512KB)
<Value>
A18
THC63LVDS83
<Value>
PD[24..47]
PVSYNC
PHSYNC
PDE
PSHFCLK
TX0-
TX0+
TX1-
TX1+
TX2-
TX2+
TX3-
TX3+
SiI161 (SiI169 FOR HDCP)
<Value>
RX0-
RX0+
RX1-
RX1+
RX2-
RX2+
RXC-
RXC+
PAR[0..7]
PAG[0..7]
PAB[0..7]
DVICK
SCDT
D D E
HSYNC_DVI
VSYNC_DVI
PDP42V5_PANEL
<Value>
TX0-
TX0+
TX1-
TX1+
TX2-
TX2+
TX3-
TX3+
SCLK
SLE
SDATA
PDP42V6_PANEL
<Value>
TX0-
TX0+
TX1-
TX1+
TX2-
TX2+
TX3-
TX3+
PENVDD
SCLK
SDATA
SLE
EL8300_1
<Value>
R
G
B
R
G
B
SDRAM1
<Value>
DATA[0..31]
ADR[0..10]
SDCL
K
CAS#
SDWE#
RAS#
AD9888
<Value>
Yin1
Vin1
Uin1
Y[0..7]
Cb[0..7]
Cr[0..7]
VSYNC2
HSYNC1
PCLK
SCL
SDA
H S
VS
SOGOUT
4052
<Value>
CTL_Y
CTL_X
HS0
HS1
HS2
HS3
VS0
VS1
VS2
VS3
HS_OUT
VS_OUT
power on reset
<Value>
RES
TB1274AF
<Value>
Y2
U2
V2
CVBS1
Y
U
V
H S
VS
Y_COM
C_COM
FSC
SDA
SCL
YS1
Y1
U1
V1
TC90A69
<Value>
Y_COM
C_COM
FSC
SDA
SCL
89C2051
<Value>
FRONT_IR
standby_sync
AC_ON
RLY_ON
5V_MONI
VsVa_ON
KEY1
KEY2
KEY3
KEY4
RF
LED_R
LED_B
PI5V330_1
<Value>
Y1
U1
V1
Y2/G
U2/B
V2/R
Y
U
V
SEL_Hd
PI5V330_2
<Value>
Y
Pb
Pr
R
G
B
Y
U
V
SEL_VGA
OSC_14.318MHZ
<Value>
CLK
FLI2310
<Value>
Y[0..7]
Cb[0..7]
Cr[0..7]
HS2
VS2
HS1
VS1
PCLK
Y_out[0..7]
Cb/Cr_out[0..7]
ADR[0..10]
DATA[0..31]
MEMCLK
O
HS_DI
VS_DI
PCLK
SCL
SDA
RESET
CAS#
SDWE#
RAS#
13.5MHZ
80C32_MCU
<Value>
P0[0..7]
INT1
SCL1
SDA1
JRD
JWR
JTEST
MCALE
TMDSPD
OE_DIG
MCA8
MCA9
SEL_A/B
INT_STB
standby_sync
SDA2
SCL2
FRONT_IR
JTEST
TXD
R X D
JAGAUM
<Value>
Y_PC[0..7]
C_PC[0..7]
PAR[0..7]
PAG[0..7]
PAB[0..7]
HSREF_PC
VSREF_PC
PCLK_PC
DVICLK_PA
R1_ANALOG
G1_ANALOG
B1_ANALOG
MCA[0..7]
INTR#
MCRD#
MCWR#
TEST
TMDSPD
MCAL
E
RESET
HS_PB
VS_PB
DE_PA
MCA8
MCA9
PD[0..23]
PVSYNC
PHSYNC
PDE
PSHFCLK
14.318
M
ADR[0..10]
DATA[0..31]
CAS#
SDWE#
RAS#
CLK_SDRA
M
VSYNC_PA
HSYNC_PA
PBR[0..7]
PBG[0..7]
PBB[0..7]
PD[24..47]
GPIO0
GPIO1
GPIO3
GPIO4
PENVDD
SDRAM2
<Value>
DATA[0..31]
ADR[0..10]
CLK
CAS#
SDWE#
RAS#
SII164
<Value>
PD[0..23]
PVSYNC
PHSYNC
PDE
PSHFCLK
TX0-
TX0+
TX1-
TX1+
TX2-
TX2+
TX3-
TX3+
SDRAM3
<Value>
DATA[0..31]
ADR[0..10]
CLK
CAS#
SDWE#
RAS#
OR1
R
OR2
R
OR3
R
ANALOG R1
RX1+
ANALOG B1
RXC-
RX2-
RX0+
ANALOG G1
RX1-
RX2+
RXC+
Cr_STB
Y_STB
Cb_STB
SCL_STB
SDA_STB
INT_STB
Y/Yd_panel/CVBS
Cr/Pr_panel
R X D
TXD
RX0-
Cb/Pb_panel
HSYNC1
VSYNC1
HS_STB
VS_STB
22
