13-Nov.2013 Ver.0.9
TAIYO YUDEN
Tentative
TAIYO YUDEN
9/16
WYSAAVDX7
Control No.
HD-AE-A100174 (2/5)
Control name
Electrical characteristics
AC Specifications
Power-on timing / External sleep clock
Parameter Condition Symbol
Min
Typ
Max
Unit
Remark
1
Valid Power / RESETn / Clock to PDn de-asserted
Tpor
300
ms
2 Input SLP_CLK frequency
Tf
32.768
KHz
3 Input SLP_CLK high voltage
V
IH
0.8 1.8
1.98 V
4 Input SLP_CLK low voltage
V
IL
0.0 0.25 V
5 Input SLP_CLK phase noise requirement
PN
-125
dBc/Hz @100KHz
6 Input SLP_CLK slew rate limit (10-90%)
SR
100
ns
7 Input SLP_CLK duty cycle tolerance
DC
20
80
%
<Power-on sequence>
PDn must remain asserted for minimum of Tpor after VBAT, VIO and SLP_CLK are stable.
RESETn must be inactive value (asserted high) when PDn is de-asserted (high level).
Tpor
PDn
VBAT
SLP_CLK
(32.768KHz)
Tf
VIO
External reset(RESETn), power down(PDn)
Parameter Condition
Symbol
Min
Typ
Max
Unit
Remark
1
RESETn pulse width
Trpw
1
ms
Note1
2
PDn pulse width
Tppw
300
ms
Notes2, 3
1. RESETn should be asserted while VBAT, VIO and SLP_CLK are stable and PDn is de-asserted (high level).
2. PDn should be asserted while VBAT, VIO and SLP_CLK are stable and RESETn is de-asserted (high level).
3. For lowest current consumption, apply all power rails to WYSAAVDX7 during the assertion of PDn pin.
