Tait TM8000 Series, Руководство по обслуживанию

Страница: 70 / 244

70 Circuit Descriptions TM8100 Mobile Radio Service Manual
May 2004 © Tait Electronics Limited
Speed-up Techniques
To reduce the change-over time between transmit and receive, part-time
speed-up techniques have been implemented. Speed-up involves
changing some resistor values while simultaneously changing the PLL IC
settings. This process is implemented in hardware under software control
in conjunction with use of the synthesized reference input. The result is
a transmit-receive settling time of less than 4.5 ms. (The switching time
is measured for a frequency change equal to the first IF plus 10 MHz or
1 MHz, depending on the repeater offsets used for the band. This
implies a synthesizer transmit-receive change-over plus an offset of
1 MHz or 10 MHz in less than 4.5 ms. The ramp-up and ramp-down
of the transmitter, which totals 1 ms, extends this change-over time to
5.5 ms.)
3.5 Frequency Control Loop
Introduction
The FCL forms part of the frequency-synthesizer module. The basis of
the FCL is a VCXO, which generates the reference frequency required
by the main PLL of the synthesizer. The FCL circuitry is given on sheet
5 of the circuit diagram for the main board, and is described below.
Elements of
FCL Circuitry
The FCL is a simple frequency-locked loop. The circuitry consists of the
following elements:
■
VCXO (XL501, Q501, Q503)
■
TCXO (XL500)
■
buffer amplifier (IC500)
■
mixer (IC501)
■
low-pass filter (IC502, pins 5 to 7)
■
modulator buffer amplifier (IC502, pins 1 to 3)
The TCXO supplies a reference frequency of 13.0000 MHz, which is
extremely stable, regardless of the temperature. The VCXO runs at a
nominal frequency of 13.0000 MHz, and is frequency-locked to the
TCXO reference frequency.
Circuit Operation
The VCXO output is mixed with the TCXO output to create a nominal
difference (or offset) frequency
SYN CDC FCL
of 12.0 kHz. The signal
SYN CDC FCL
is fed via the CODEC IC502 in the CODEC circuitry to
the FPGA on the digital board. The FPGA detects the offset frequency,
compares it with the programmed offset frequency, and outputs a
corresponding feedback signal
CDC VCXO MOD
via IC205. The feedback
signal is amplified and inverted by the modulator buffer amplifier and
output as the loop voltage for the VCXO. With this design the VCXO
frequency can be adjusted by very small precise amounts, and because the
loop is locked, the VCXO inherits the temperature stability of the
TCXO.