DWC ADC 12b5M SAR, TSMC180 IP Databook
April 2012
Synopsys, Inc.
24-30
System Level Clock Issues
To avoid compromising the SAR ADC performance, one should minimize the digital
switching activity near its sampling instant. This is accomplished by:
1. Increasing, as much as possible, the time between the sampling instant and the clock
edges where there is activity in the digital core(s).
2. Increasing, as much as possible, the time between the sampling instant and the
activity on the output pads.
A good quality low jitter clock must be provided to avoid degrading the SAR ADC
performance.
Routing of Analog and Reference Signals
Due to the analog nature of this block, the routing should be done carefully and according to
the following rules:
Keep all analog signal routing as small as possible.
Shield all critical analog signals, specially the single-ended ones, using the analog
ground (
agnd
).
Take special attention to the routing of the input lines. Any noise coupling is treated as
input signal, thus reducing the dynamic range of the cell.
Keep all analog, reference and power supply lines with the width (at least) equal to the
respective core cell pin width. Respect the maximum wire resistance values mentioned
in
Cell Routing Constrains
section; if necessary increase the line width or use several
metal layers.
Use as many vias as possible when changing between metal layers.
Follow the indications given in the
Connections to the IO Pad Ring
section.
ESD / Latch-Up
All input / output elements connecting directly to pads are designed with standard secondary
protection device structure. Primary ESD protection is always required at IO PAD level.
Analog pads should
not
have a series resistance, in order not to deteriorate performance.
Each technology or IO PAD ESD guidelines must, obviously, be respected despite that
section 10 generic IO Placement example.