DWC ADC 12b5M SAR, TSMC180 IP Databook
April 2012
Synopsys, Inc.
11-30
If the offset is not a critical parameter, there is no need to run the calibration cycle.
However, there is the need to start a dummy conversion cycle (by setting
soc
=H, as
described in Section 7), before the ADC is ready to receive analog inputs;
8. In situations where the
avdd
supply is active and the
dvdd
supply is not active (not
supplied), the ADC may develop excessive leakage current. If the
dvdd
is left
unpowered for extended periods and this leakage power becomes a concern, it can
be eliminated by asserting
dislvl
=H until the
dvdd
supply is ramped up. Once the
dvdd
supply goes to its nominal range,
dislvl
can be set to low.
Note that the
dislvl
digital input signal must have 3.3 V levels (
avdd
).
Deep power down mode
The deep power down mode enables the user to reduce the leakage current to the absolute
minimum, by switching off the supply of the digital calibration block (
dvdd
). In this mode all
digital outputs are set to
low
.
The deep power down mode is controlled by the signal
dislvl
=H, in addition to the
enadc
=L
and
enldo
=L already used in the normal power down mode. In this mode, all internal register
(calibration register) values will be lost. It is therefore advisable to store the calibration word
(available through
bvos6
…0
bus before entering deep power down mode.
The startup sequence from deep power down should be as follows
0. Set
dislvl
=L;
1. Set
enldo
=H and wait for the internal voltage regulator start-up;
2. Set the
resetcal
signal to
high
during one clock cycle. There is no need to wait for the
internal voltage regulator start-up time to set
resetcal
to
high
. This signal can be set
to
high
right after the power supplies are stable. The only demand is to set it to
high
during one clock cycle before the next step (
enadc
=H);
3. Set
enadc
=H;
4. Set the
resetadc
signal to
high
during one clock cycle;
5. Ensure that the calibration word is valid at the inputs
bvosi6
…0
during one clock
cycle after the release of reset signals, and set
loadcal
=H during one clock cycle, in
order to read back the calibration value into the internal registers (for a better
understanding please check Figure 5 and 12);
6. Run dummy conversion cycle, the ADC is ready to receive the analog signal.
If the ADC is in deep power down for extended periods, then it is recommended that a new
calibration cycle is run at power up time.
The dummy conversion cycle can be started simultaneously with the loading of the
calibration word (step 5 above).
Power-down Mode
The power down mode is obtained by setting
enadc
=L and
enldo
=L.
While the ADC is in power down mode, the calibration coefficients are kept in the internal
registers of the ADC. In this way, the ADC can be brought back from power down and a