Synopsys DesignWare ARC AXC003, Руководство пользователя, Страница: 9 / 145

9
Version 6323-018 Synopsys, Inc.
May 2017
List of Tables
Table 1 Self-Test Start Buttons .................................................................................................................... 20
Table 2 Characters on the Seven-Segment Display During the Self-Test ................................................... 21
Table 3 Jumper Functionality ....................................................................................................................... 31
Table 4 LED Control Bits .............................................................................................................................. 33
Table 5 Control Bits of the Seven-Segment Displays .................................................................................. 35
Table 6 Main Features of the ARC Cores .................................................................................................... 36
Table 7 Interrupt Mapping for ARC HS36 .................................................................................................... 43
Table 8 Interrupt Mapping for ARC HS38 .................................................................................................... 44
Table 9 Mainboard ICTL Interrupt Mapping ................................................................................................. 45
Table 10 Clock Frequencies .......................................................................................................................... 48
Table 11 JTAG ID Codes ............................................................................................................................... 49
Table 12 Control Register Memory Map ........................................................................................................ 50
Table 13 GPIO Register Memory Map ........................................................................................................... 52
Table 14 GPIO Port A Output Register Bit Function (SWPORTA_DR) ......................................................... 52
Table 15 GPIO port A Input Register Function (EXT_PORTA) ...................................................................... 53
Table 16 GPIO port B Output Register Function (SWPORTB_DR) ............................................................... 54
Table 17 GPIO port B input register function (EXT_PORTB) ........................................................................ 55
Table 18 Memory mapping for ARC HS36 ..................................................................................................... 56
Table 19 Memory mapping for HS34 Emulation ............................................................................................ 57
Table 20 Pinout of the Power-Supply Connector ........................................................................................... 58
Table 21 ARC Core Boot Configuration (Mainboard DIP Switch SW2501) ................................................... 60
Table 22 Multicore Configuration (Mainboard DIP Switch SW2503) ............................................................. 61
Table 23 Usage of the CPU Start Buttons of the ARC SDP Mainboard ........................................................ 63
Table 24 Control Bits of the CPU LEDs on the ARC SDP Mainboard ........................................................... 64
Table 25 ARC CPU Memory Map After Pre-Bootloader Execution ............................................................... 65
Table 26 AXI Tunnel Memory Map After Pre-Bootloader Execution (ARC HS34 / HS36) ............................. 67
Table 27 AXI Tunnel Memory Map After Pre-Bootloader Execution (ARC HS38) ......................................... 67
Table 28 AXC003 CPU Card Target Slaves .................................................................................................. 68
Table 29 ARC SDP Mainboard Target Slaves ............................................................................................... 68
Table 30 ARC CPU Memory Map Pre-Boot Programming on the AXC003 CPU Card ................................. 69
Table 31 Memory Map Pre-Boot Programming for All Masters on the ARC SDP Mainboard ....................... 70
Table 32 Peripheral Memory Map .................................................................................................................. 71
Table 33 Meaning of the Left Character of the Seven-Segment Display ....................................................... 76
Table 34 Meaning of the Right Character of the Seven-Segment Display ..................................................... 77
Table 35 baremetal Folder Contents .............................................................................................................. 78
Table 36 Build Options ................................................................................................................................... 81
Table 37 Command Line Options for build.bat ............................................................................................... 83
Table 38 CPU Start Buttons and Display Values for Running Applications in the Debugger ........................ 87
Table 39 Property Arguments for Selecting the CPU Core in the Debugger ................................................. 91
Table 40 MQX folder Contents ....................................................................................................................... 97
Table 41 GPIO port A Output Register (GPIO_SWPORTA_DR) ................................................................. 127
Table 42 GPIO port B output Register (GPIO_SWPORTB_DR) ................................................................. 128
Table 43 GPIO Port A Input Register (GPIO_EXT_PORTA) ....................................................................... 129
Table 44 GPIO Port B Input Register (GPIO_EXT_PORTB) ....................................................................... 130