Synopsys DesignWare ARC AXC003, Руководство пользователя, Страница: 50 / 145

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DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview
Synopsys, Inc. Version 6323-018
May 2017
Control Registers
The CREG peripheral inside the AXC003 Processor FPGA provides software registers to
control the following features:
System memory map (see System Memory Map on page 65)
Boot mode (see Boot Modes on page 72)
Table 12 lists the control registers and provides the address offsets to the base address of
the AXI2APB segment in the system memory map. By default the base address of the
AXI2APB segment is 0xF000_0000 (see
System Memory Map After Pre-Bootloader
Execution on page 65).
For a detailed description of the control registers, see Software Interfaces on page 108.
Table 12 Control Register Memory Map
Name Address Offset R/W Description
Clock Generation Registers
TUN_PLL_IDIV 0x0000_0040 RW
Tunnel input divider register
TUN_PLL_FBIDIV 0x0000_0044 RW
Tunnel feedback divider
register
TUN_PLL_ODIV 0x0000_0048 RW
Tunnel output divider register
ARC_PLL_IDIV 0x0000_0080 RW
ARC input divider register
ARC_PLL_FBIDIV 0x0000_0084 RW
ARC feedback divider register
ARC_PLL_ODIV 0x0000_0088 RW
ARC output divider register
TUN_PLL_LOCK 0x0000_0108 R
Tunnel PLL lock register
ARC_PLL_LOCK 0x0000_0110 R
ARC PLL lock register
AXI Tunnel Address Decoder Registers
TUN_A_SLV_SEL0 0x0000_1000 RW
Slave select register for AXI
tunnel
TUN_A_SLV_SEL1 0x0000_1004 RW
Slave select register for AXI
tunnel
TUN_A_SLV_OFFSET0 0x0000_1008 RW
Address offset register for AXI
tunnel
TUN_A_SLV_OFFSET1 0x0000_100C RW
Address offset register for AXI
tunnel
TUN_A_UPDATE 0x0000_1014 RW1C
Address decoder update
register for AXI tunnel