48
DesignWare ARC AXC003 CPU Card User Guide
AXC003 Processor FPGA Overview
Synopsys, Inc.
Version 6323-018
May 2017
Table 10
Clock Frequencies
PLL
Clock
Clk Frequency (MHz)
Run-Time
Programmable
Maximu
m
After Reset
After Pre-
Boot
AMBA
apb_clk
100
100
100
No
axi_clk
100
100
100
No
DDR
ddr_ref_clk
133
133
133
No
TUNNEL
tunnel_clk
100
50
100
Yes
UART
uart_ref_clk
33
33
33
No
ARC
arc_clk
100 /
50
100
Yes
1) Fmax for HS36 and HS38x2
Reset
The AXC003 Processor FPGA has one external reset pin (
rst_n_in
) that serves as an
active low, hardware reset. When the external hardware reset is active, the entire FPGA is
reset. This pin is routed to the HapsTrak II connector and controlled by reset circuitry on the
ARC SDP Mainboard, which also implements the power-on-reset. The CGU on the AXC003
Processor FPGA performs reset synchronization to the internal clock domains.
Use the
Reset
button on the ARC SDP Mainboard to trigger a reset of the entire system.
Location of the RESET Button on the ARC SDP Mainboard
The AXC003 Processor FPGA has an external reset output pin (
rst_n_out
), which is
routed to the HapsTrak II connector as well. This reset output is used by the reset controller
on the ARC SDP Mainboard.