Synopsys DesignWare ARC AXC003, Руководство пользователя, Страница: 52 / 145

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DesignWare ARC AXC003 CPU Card User Guide AXC003 Processor FPGA Overview
Synopsys, Inc. Version 6323-018
May 2017
Name Address Offset R/W Description
AXI Tunnel Registers
TUN_CTRL 0x0000_14A0 RW
AXI tunnel control register
TUN_STAT 0x0000_14A4 R
AXI tunnel status register
GPIO Registers
The GPIO peripheral in the AXC003 Processor FPGA uses DesignWare
dw_apb_gpio
IP
[3] and provides two GPIO ports.
Table 13 lists the GPIO registers and provides the address offsets to the base address of the
AXI2APB section in the system memory map.
By default the base address of the AXI2APB segment is
0xF000_0000
(see System Memory
Map After Pre-Bootloader Execution on page 65). Table 14
describes the function of the GPIO
bits.
Table 13 GPIO Register Memory Map
Name Address
Offset R/W Description
GPIO_SWPORTA_DR 0x3000
R/W Port A Data Register
Controls LEDs on the ARC SDP Mainboard
GPIO_EXT_PORTA 0x3050
R External Port A Register
Input from CPU Start buttons on the ARC SDP
Mainboard and from the Mainboard
’s interrupt
request
GPIO_SWPORTB_DR 0x300C
R/W Port B Data Register
Controls LEDs and seven-segment displays on
the AXC003 CPU Card
GPIO_EXT_PORTB 0x3054
R External Port B Register
Input from jumpers on the AXC003 CPU Card
Table 14 below and Table 15 on page 53 describe the function of the Port A registers. Table
16 on page 54 and Table 17 on page 55 describe the Port B registers.
Table 14 GPIO Port A Output Register Bit Function (SWPORTA_DR)
Bit Description
0
Connected to LED2501 of the ARC SDP Mainboard
The LED is ON when this bit is set to
1
.