Supero X9DR7-TF+, Руководство пользователя

Страница: 57 / 117

Chapter 2: Installation
2-33
JS
3
LEM1
SW1
JSTBY1
JBR1 JWD1
JPG1
JPB1
JPL1
JPS1
JWP1
JPME
1
JPME
2
LE
2
JBT1
J2
1
JTPM
1
JIPMB1
FA
N6
FAN5
FA
NB
FA
NA
FA
N4
FA
N3
FA
N2
FAN1
JI2C
1
JOH
1
JI2C
2
JP
6
JL1
JBAT1
J1
7
SP1
JSD1
JPW1
JPW2
JPI2C1
JD
1
JF1
X9DR7-TF+
Rev. 1.00
BBU
CPU2 SLOT3 PCI-E 3.0 X1
6
I-S
AT
A4
L-SAS 4~7
CPU1 SLOT4 PCI-E 3.0 X8 CPU1 SLOT1 PCI-E 3.0 X8
XDP-CPU
CPU1 SLOT2 PCI-E 3.0 X8
USB9
I-SATA3
I-S
AT
A1
COM2
USB6/7
USB4/5
I-S
AT
A2
I-S
AT
A0
CPU2 SLOT6 PCI-E 3.0 X8 CPU2 SLOT5 PCI-E 3.0 X1
6
I-S
AT
A5
L-SAS 0~3
UID
VGA
LAN2
P1 DIMMC
1
P1 DIMMC
2
P1 DIMMC
3
P1 DIMMD
1
P1 DIMMD
2
P1 DIMMD
3
LAN1
P1 DIMMB
3
P1 DIMMB
2
P1 DIMMB
1
P2 DIMME
1
P2 DIMME2
P1 DIMMA
3
P1 DIMMA
2
P2 DIMME3 P2 DIMMF
1
P1 DIMMA
1
P2 DIMMF3 P2 DIMMF
2
P2 DIMMH
3
P2 DIMMH
2
P2 DIMMH
1
P2 DIMMG
3
P2 DIMMG1 P2 DIMMG
2
USB2&3 USB0&1
IPMI_LAN
KB/Mouse
COM1
JPW3
LE1
JP
7
J1
8
DS1
DS3
DS2
LEDS
1
LEDS
2
CPU2
CPU1
Battery
BMC
CTRL
CTRL
LAN
PCH
CTRL
SAS
JRK1
A
B
A. T-SGPIO1
B. T-SGPIO2
C. DOM PWR
T-SGPIO 1/2 Headers
Two SGPIO (Serial-Link General
Purpose Input/Output) headers are lo-
cated at J17/J18 on the motherboard.
These headers support Serial_Link
interface for onboard SATA connec-
tions. See the table on the right for
pin definitions.
Note: NC= No Connection
T-SGPIO
Pin Definitions
Pin# Definition Pin Definition
2 NC 1 NC
4 Ground 3 Data
6 Load 5 Ground
8 Clock 7 NC
C
DOM Power Connector
A power connector for SATA DOM
(Disk_On_Module) devices is located
at JSD1. Connect an appropriate
cable here to provide power support
for your DOM devices.
DOM PWR
Pin Definitions
Pin# Definition
1 +5V
2 Ground
3 Ground