Supero SuperServer 6033P-8R, Руководство пользователя

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UPER
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ERVER 6033P-8R Manual
1-2
1-2 Serverboard Features
At the heart of the SuperServer 6033P-8R lies the X5DP8-G2, a dual Intel Xeon
processor serverboard designed to provide maximum performance. Below are the
main features of the X5DP8-G2.
Chipset
The X5DP8-G2 is based on Intel's E7501 chipset, which is a high-performance
core logic chipset designed for dual-processor servers. See Figure 1-1 for a
block diagram of the E7501.
The E7501 chipset consists of four major components: the Memory Controller
Hub (MCH), the I/O Controller Hub 3 (ICH3), the PCI-X 64-bit Hub 2.0 (P64H2) and
the 82808AA Host Channel Adapter (VxB).
The MCH has four hub interfaces, one to communicate with the ICH3 and three
for high-speed I/O communications. The MCH employs a 144-bit wide memory
bus for a PC1600 (DDR-200) memory interface, which provides a total bandwidth
of 3.2 GB/s. The ICH3 interface is a 266 MB/sec point-to-point connection using
an 8-bit wide, 66 MHz base clock at a 4x data transfer rate. The P64H2 interface
is a 1 GB/s point-to-point connection using a 16-bit wide, 66 MHz base clock at
a 8x data transfer rate.
The ICH3 I/O Controller Hub provides various integrated functions, including a
two-channel UDMA100 bus master IDE controller, USB host controllers, an in-
tegrated LAN controller, a System Management Bus controller and an
AC'97 compliant interface.
Each P64H2 PCI-X Hub (there are two) provides a 16-bit connection to the
MCH for high-performance IO capability and the 64-bit PCI-X interface.