BIOS Manual
B-2
APPENDIX B
C h e c k
Point
Description
10
T h e k e y b o a r d c o n t r o l l e r c o m m a n d b y t e i s w r i t t e n .
Next, issuing the pin 23 and 24 blocking and unblocking
commands.
11
Next, checking if the <End or <Ins> keys were pressed
d u r i n g p o w e r o n . I n i t i a l i z i n g C M O S R A M i f t h e
I n i t i a l i z e C M O S R A M i n e v e r y b o o t A M I B I O S P O S T
o p t i o n w a s s e t i n A M I B C P o r t h e < E n d > k e y w a s
pressed.
12
Next, disabling DMA controllers 1 and 2 and interrupt
controllers 1 and 2.
13
The video display has been disabled. Port B has been
initialized. Next, initializing the chipset.
14
The 8254 timer test will begin next.
19
The 8254 timer test is over. Starting the memory refresh
test next.
1A
The memory refresh test line is toggling. Checking the
15 second on/off time next.
23
R e a d i n g t h e 8 0 4 2 i n p u t p o r t a n d d i s a b l i n g t h e
M E G A K E Y G r e e n P C f e a t u r e n e x t . M a k i n g t h e
B I O S c o d e s e g m e n t w r i t a b l e a n d p e r f o r m i n g a n y
necessary configuration before initializing the interrupt
vectors.
24
T h e c o n f i g u r a t i o n r e q u i r e d b e f o r e i n t e r r u p t v e c t o r
initialization has completed. Interrupt vector initialization
i s d o n e . C l e a r i n g t h e p a s s w o r d i f t h e P O S T D I A G
switch is on.
25
I n t e r r u p t v e c t o r i n i t i a l i z a t i o n i s d o n e . C l e a r i n g t h e
password if the POST DIAG Switch is on.
27
A n y i n i t i a l i z a t i o n b e f o r e s e t t i n g v i d e o m o d e w i l l b e
done next.
Содержание SUPER P6SWA
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