Chapter 4: AMI BIOS
4-7
BCLK Aware Adaptive Voltage
When enabled, pcode will be aware of the BCLK frequency when cal-
culating the CPV/F curves. This is ideal for BCLK to avoid high voltage
overrides. The options are Disabled or
Enabled
.
RSR
This item enables or disables the RSR feature. The options are
Disabled
or Enabled.
Intel(R) SpeedStep(tm)
Enhanced Intel SpeedStep Technology (EIST) allows the system to
automatically adjust processor voltage and core frequency in an effort
to reduce power consumption and heat dissipation.
Please refer to
Intel’s website for detailed information.
The options are Disabled
or
Enabled
.
Turbo Mode
This feature allows processor cores to run faster than the frequency rec-
ommended by the manufacturer. The options are Disabled or
Enabled.
Package Power Limit MSR Lock
This feature enables or disables the locking of Package Power Limit
settings. When enabled, Package Power Limit MSR will be locked and a
reset will be required to unlock the register. The options are
Disabled
or Enabled.
Configurable TDP Boot Mode
This feature sets the TDP Boot Mode to either
Nominal
, Down, Up, or De-
activate. When deactivated, it will set MSR to Nominal and MMIO to zero.
Configurable TDP Lock
This feature sets the lock bits on TURBO_ACTIVATION_RATIO and CON-
FIG_TDP_CONTROL. When lock is enabled, Custom Config TDP Count
will be forced to 1 and Custom Config TDP Boot Index will be forced to
0. The options are
Disabled
or Enabled.
CTDP BIOS Control
This feature enables CTDP control via runtime ACPI BIOS methods. The
options are
Disabled
or Enabled.
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