Supermicro X6DHR-X8G, Руководство пользователя

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X6DHR-X8G/X6DHR-XiG User's Manual
ICH5R
( S o u t h
Bridge)
7 9 0 2
S C S I
C T R L
C
SI Ch A
W O L
COM2
Fan3
S C S I
E n a b l e
F P U S B 0 / 1
J D 2
CLR CMOS
W O R
S P K
S W
SCSI Ter. A
JPA1
JBT1
P W
L E D
CH
I n t
J L 1 J W D
W D
JP11
Alarm
S W
JPA3
JPA2
SCSI Ter. B
OH
J D 1
J A 1
Firmware
H u b
JP10
K B
DI
M
ouse
U
SB
0/1
J 1 4
C
O
M
1
DI
DI
DI
DI
DI
DI
DI
J 3 3
J 3 4
J 1 6
K B
DIMM 4B
M
o
u
s
e
U
S
B
0
/1
J 1 4
C
O
M
1
DIMM 4A
DIMM 3B
DIMM 3A
DIMM 2B
DIMM 2A
DIMM 1B
DIMM 1A
GLAN1
GLAN2
V
G
A
S
C
S
I C
h B
Battery
JPG1(VGA Enable)
JPL1(LAN Enable)
RAGE-
X
GLAN
C T R L
P X H
P X H
PCI-X
PCI-X
E 7 5 2 0
(North Bridge)
ICH5R
( S o u t h
Bridge)
Z C R
IPMI 2.0
BIOS
S I/O
7 9 0 2
S C S I
C T R L
IDE #1
IDE #2
Floppy
SCSI Ch A
W O L
C
O
M
2
Fan
S C S I
E n a b l e
F P U S B 0 / 1
J D 2
J P 9
CLR CMOS
Force PW-On
W O R
S P K
S W
S
C
S
I
Te
r. A
JPA1
JBT1
S
M
B
F
A
N
5
S
A
T
A
1
S
A
T
A
0
F
P
C
T
R
L
J
F
1
F A N 2
F A N 1
2 0 - P i n P W
8-Pin
C P U 4-Pin
P W
PW SMB
P W
L E D
CH
I n t
J L 1 J W D
W D
CPU1
CPU2
JP11
Alarm
S W
JPA3
JPA2
SCSI Ter. B
OH
J 3 3
J 3 4
J 1 6
L
G
5
J14
J D 1
J A 1
J 5
J 6 J 1 2
F
A
N
4
Firmware
H u b
J1B1
J1D1
J 3 8
J 3 2
J4
F
4
J
4
F
5
M
e
m
o
ry
S
p
e
e
d
(*N
o
te
:4
)
J
1
1
P W
F a i l
JP10
S P K R
Universal Serial Bus
(USB0/1)
Two USB 2.0 ports (J16) are lo-
cated beside the Mouse and COM1
ports. USB0 is the bottom connec-
tor and USB1 is the top connector.
See the table on the right for pin
definitions.
Universal Serial Bus Pin Definitions
Pin
Number
Definition
1 +5V
2 P0-
3 P0+
4 G round
5 N/A
Pin
Number
Definition
1 +5V
2 P0-
3 P0+
4 G round
5 Key
US B0
US B1
Chassis Intrusion
A Chassis Intrusion header is lo-
cated at JL1. Attach the appropri-
ate cable to inform you of a chas-
sis intrusion.
C h a s s
Intru
USB
0/1