61
Chapter 2: Installation
BAR CODE
DESIGNED IN USA
MAC CODE
X12DAi-N
REV:1.01
BIOS LICENSE
JM2_2
MH18
MH17
JM2_1
MH16
MH15
HEARTBEAT
BMC
FANA
JBT1
T-SGPIO2
T-SGPIO1
BT1
JPWR3
J37
SA
TA4
SA
TA6
SA
TA5
SA
TA8
SA
TA7
SA
TA1
SA
TA3
SA
TA2
JPWR2
JPWR1
JPWR4
JPR
G1
JNVI2C
JP
ME1
JPL1
JWD1
JPL2
JD1
JVRM1
JVRM2
JL1
JSPDIF_IN1
JSPDIF_OUT1
JTP
M1
JA1
JRK1
LEDM1
LE4
LE7
JPI2C1
JVGA
FAN1
FAN2
FAN5
FAN6
FAN3
FAN4
FAN7
JNCSI
JNVME1
JNVME2
JPCIE5
JPCIE4
JPCIE3
JPCIE2
JPCIE1
JF1
JUSBA
JSD1 JSD2
JUSB1
JP7
JUSB31_I1
JLAN1
JPCIE6
JAUDIO1
JIPMB1
RAID KE
Y-1
I-SA
TA5
I-SA
TA4
I-SA
TA3
I-SA
TA2
I-SA
TA1
I-SA
TA0
I-SATA6 I-SATA7
LAN/1/2
HD A
UDIO
P2_NVME0/1
USB7(3.1)
LED
PWR
USB4(3.1)
P1_NVME0/1
USB5/6(3.0)
USB0/1/2/3(3.0)
VGA
COM1
CMOS CLEAR
TP
M/POR
T80
JTP
M1:
P1-DIMMB1
P1-DIMM
A1
P1-DIMMD1
P1-DIMMC1
P1-DIMMG1
P1-DIMMF1 P1-DIMME1 P1-DIMMH1
P2-DIMMG1
P2-DIMMC1
P2-DIMMD1
P2-DIMMB1 P2-DIMM
A1
P2-DIMME1 P2-DIMMF1
P2-DIMMH1
CPU2
CPU1
CPU1 SL
O
T1 PCI-E 4.0 X16
CPU2 SL
O
T2 PCI-E 4.0 X16
CPU1 SL
O
T3 PCI-E 4.0 X16
CPU2 SL
O
T4 PCI-E 4.0 X16
CPU1 SL
O
T5 PCI-E 4.0 X16
CPU2 SL
O
T6 PCI-E 4.0 X8
PCH
SGPIO Headers
There are two Serial_Link General Purpose Input/Output (I-SGPIO1 and I-SGPIO2) headers
located on the motherboard. I-SGPIO is used for communicate with the enclosure management
chip on the backplane. Refer to the tables below for pin definitions.
SGPIO Header
Pin Definitions
Pin#
Definition
Pin#
Definition
1
NC
2
NC
3
Ground
4
Data
5
Load
6
Ground
7
Clock
8
NC
NC = No Connection
Disk-On-Module Power Connector
Two power connectors for SATA DOM (Disk-On-Module) devices are located at JSD1 and
JSD2. Connect appropriate cables here to provide power support for your Serial Link DOM
devices.
DOM Power
Pin Definitions
Pin#
Definition
1
5V
2
Ground
3
Ground
1
2
3
4
1. I-SGPIO1
2. I-SGPIO2
3. JSD1 (DOM PWR)
4. JSD2 (DOM PWR)
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