Supermicro SUPERSERVER 5018A-TN7B, Руководство пользователя

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Chapter 7: AMI BIOS
7-13
ECC (Error Correctable Correction)
Select Enabled to enable ECC support. The options are Enabled and Disabled.
Faulty Part Tracking
Select Enabled to support faulty part tracking for the system to keep track of faulty
memory parts. The options are
Disabled and Enabled.
On Correctable Faulty Part
This feature displays the status of "On Correctable Faulty Part".
Patrol Scrub Enable
Patrol Scrubbing is a process that allows the CPU to correct correctable memory
errors detected on a memory module and send the correction to the requestor
(the original source). When this item is set to Enabled, North Bridge will read and
write back one cache line every 16K cycles, if there is no delay caused by internal
processing. By using this method, roughly 64 GB of memory behind North Bridge
will be scrubbed every day. The options are Disabled and
Enabled .
Patrol Scrub Period
Use this item to specify how often Patrol Scrubbing should be performed. Select 24
hours to allow Patrol Scrubbing to be performed every 24 hours. The options are
24 hours, 10 hours, 4 hours, and 1 hour.
Demand Scrub Enable
Demand Scrubbing is a process that allows the CPU to correct correctable memory
errors found on a memory module. When the CPU or I/O issues a demand-read
command, and the read data from memory turns out to be a correctable error, the
error will be corrected and sent to the requestor (the original source). Memory will
be updated at the same time. Select Enabled to use Demand Scrubbing for ECC
memory correction. The options are
Enabled and Disabled.
AB Segments In DRAM
When this feature is set to Enabled, Target A- or B- segments will be routed to
DRAM during memory read and write cycles. The options are Enabled and
Dis-
abled .
E Segment In DRAM
When this feature is set to Enabled, Target E segment will be routed to DRAM during
memory read and write cycles. The options are
Enabled and Disabled.
F Segment In DRAM
When this feature is set to Enabled, Target F segment will be routed to DRAM during
memory read and write cycles. The options are
Enabled and Disabled.