Super B11SCG-ZTF/CTF User's Manual
58
CPU Configuration
The following information is displayed in this section:
•
CPU Signature
-
the processor identification code
•
Microcode Patch
-
the microcode revision number
•
CPU Speed
-
the approximate CPU speed
•
L1 Data Cache -
the size of the L1 data cache (if supported)
•
L1 Instruction Cache -
the size of the L1 instruction cache (if supported)
•
L2 Cache -
the size of the L2 cache (if supported)
•
L3 Cache -
the size of the L3 cache (if supported)
•
L4 Cache -
the size of the L4 cache (if supported)
•
VMX
-
displays whether VMX is supported
•
SMX/TXT
-
displays whether SMX/TXT is supported
Internal Graphics
This feature to enable or disable IGFX based on setup options. The options are Disabled
and Enabled.
C6DRAM
This feature enables moving DRAM contents to PRM memory when the CPU is in a C6 state.
The options are Disabled or
Enabled
.
CPU Flex Ratio Override
Select Enabled to activate CPU Flex Ratio programming. The options are
Disabled
or
Enabled.
*If the feature above is set to Enabled, "CPU Flex Ratio Settings" will become available
for configuration.
CPU Flex Ratio Settings
When CPU Flex Ratio Override is enabled, this sets the value for the CPU Flex Ratio. The
default is
38
.
Hardware Prefetcher
If set to Enabled, the hardware prefetcher will prefetch streams of data and instructions from
the main memory to the L2 cache to improve CPU performance. The options are Disabled
or
Enabled
.
Adjacent Cache Line Prefetch
Select Enabled for the CPU to prefetch both cache lines for 128 bytes as comprised. Select
Disabled for the CPU to prefetch both cache lines for 64 bytes. The options are Disabled or
Enabled
.
