Supermicro 8015C-T, Руководство пользователя

Страница: 75 / 118

Chapter 7: BIOS
7-9
NorthBridge Confi guration
This feature allows the user to confi gure the NorthBridge Chipset settings.
Crystal Beach/DMA
This feature uses the Intel I/O AT (Acceleration Technology) to accelerate the
performance of TOE devices. Note : A TOE device is a specialized, dedicated
processor that is installed on an add-on card or a network card to handle some
or all packet processing of this add-on card. For this motherboard, the TOE
device is built inside the ESB 2 South Bridge chip. The options are Enabled
and Disabled.
MCH (Memory Controller Hub) Branch Mode
This feature allows the user to decide how the two memory branches operate.
System address space can either be interleaved between the two branches or
sequencing from one branch to another. Mirror mode allows data correction by
maintaining two copies of data in two branches. Single Channel 0 allows a single
DIMM population during system manufacturing. The options are Interleave ,
Sequencing, Mirroring, and Single Channel 0.
Patrol Scrubbing
Scrubbing is a process that allows the northbridge to correct correctable memory
errors found on FBD memory modules. Select Enabled to use Patrol Scrubbing,
a background ECC memory correction activity initiated by the northbridge to fi nd
and correct memory errors by scanning all memory modules doing simulated
"READs" while checking for ECC errors. When an ECC error is detected during
this process, it is logged as a Patrol error. A correctable error is corrected and
written back into memory. The options are Enabled and Disabled.
Demand Scrubbing
Scrubbing is a process that allows the northbridge to correct correctable
memory errors found on an FBD memory module. When the CPU or I/O issues
a demand- read command, and the read data from memory turns out to be
a correctable ECC, it is corrected and sent to the original source. Memory is
updated as well. Select Enabled to use Demand Scrubbing for ECC memory
correction. The options are Enabled and Disabled.
Branch 0 Rank Sparing/Branch 1 Rank Sparing
Select Enable to enable the sparing feature for Branch 0 or Branch 1 of the
memory bus. The options are Enabled and Disabled .
Branch 0 Rank Interleaving/Branch 1 Rank Interleaving
Select Enable to enable the functions of Memory Interleaving for Branch 0 Rank
or Branch 1 Rank. The options for Memory Interleaving are 1:1, 2:1 and 4:1 .