Version 1.3
Page 11 of 36
SMT332/372 User Manual
Interrupts
The interrupts to the ‘C6x01 can be produced by
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comm port status change
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DMA completion
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FIFO flag status change
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external IIOF and TCLK signals present on the TIM connector
There are two registers that control the interrupt enabling. Interrupt Control register A
(ICRA) provides the first stage of interrupt selection, followed by Interrupt Control
Register B (ICRB).
When interrupts are enabled, they will be generated for every comm port word
received or transmitted (as appropriate). The selection of fast or slow interrupts
requires understanding of the timings between the STRB and RDY signals on the
comm port. Slow interrupts are generated when the fourth STRB of a word transfer
goes high. At some point after this the ‘C6x01 External Memory Interface strobe
(nCE1) becomes active. However, to allow the comm port data transfer to be
speeded up, the fast interrupts are generated on the second STRB going high. This
assumes the fourth STRB and RDY arrive before the ‘C6x01 has reacted to the early
interrupt. This is normally the case, but if the comm port is being connected to a slow
peripheral which does not guarantee the arrival of the last two comm port strobes,
then data errors may result. These enable signals can be delayed by writing to the
EMIF CE1 space control register. Warning - if fast interrupts are used and the enable
signal goes low too early this could result in the transfer hanging or incorrect data
transfer.
