Preliminary
Page 17 of 17
SMT327 User Guide
Document Name:
User Guide
Issue : 01
Rev 02
Product Name:
SMT327
Revision Date:
8 August, 2000
Author:
Bill Blyth
Original Date:
30 April 1998
9.4 Interrupt Control Register (Offset 18h)
This write-only register controls the generation of interrupts on the PCI bus. Each interrupt source has an
associated enable and clear flag. This register can be written with the contents of bits 7:0 of the Status
Register.
Enable Group
Bit
7
6
5
4
3
2
1
0
Name
CLEAR
C40 INT
0
CLEAR
IBF INT
CLEAR
OBE
INT
C40 IE
TBC IE
IBF IE
OBE IE
IBF IE
Input Buffer Full Interrupt Enable. Allows an interrupt to be generated
when the host comport input register is loaded with data from the C40.
OBE IE
Output Buffer Empty Interrupt. Allows an interrupt to be generated when
the host comport register has transmitted its contents.
TBC IE
Test Bus Controller Interrupt Enable. Interrupts from the Texas JTAG
controller are enabled when set.
C40 IE
C40 Interrupt Enable. Allows a programmed interrupt to be generated by
the C40 when set.
CLEAR
OBE INT
Write a one to this bit to clear the interrupt resulting from a comport
output event.
CLEAR
IBF INT
Write a one to this bit to clear the interrupt event resulting from comport
input.
CLEAR
C40 INT
Write a one to this bit to clear down the C40 INT event.
The JTAG controller which generates TBC INT must be cleared of all interrupt sources in order to clear the
interrupt.
9.5 Test Bus Controller-TBC (Offsets 80h-AFh)
Refer to the Texas 74ACT8990 data manual for register usage.
The clock for the TBC is ½
the PCI clock rate. So for a standard PCI slot this will therefore clock the
74ATC8990 at 16.67 MHz approximately.
The offsets and write / read capability of all TBC registers is shown below.
