Preliminary
Page 2 of 2
SMT327 User Guide
Document Name:
User Guide
Issue : 01
Rev 02
Product Name:
SMT327
Revision Date:
8 August, 2000
Author:
Bill Blyth
Original Date:
30 April 1998
SMT327
User Guide Contents
1. INTRODUCTION.....................................................................................................................................................................4
1.1 F
EATURES OF THE
SMT327.............................................................................................................................................4
2. INSTALLATION......................................................................................................................................................................5
3. ARCHITECTURAL OVERVIEW ..........................................................................................................................................6
4. PATCH AREA ARCHITECTURE. ........................................................................................................................................7
5. FRONT PANEL CONFIGURATION....................................................................................................................................9
6. BUFFERED COMMUNICATION PORTS........................................................................................................................ 10
7. JTAG INPUT & OUTPUT PORTS .................................................................................................................................... 11
8. FMS CONNECTORS (INTERNAL COMMUNICATION PORTS)............................................................................. 13
9. REGISTERS ........................................................................................................................................................................... 14
9.1 C
OMPORT
R
EGISTERS
(O
FFSET
10
H
)............................................................................................................................14
9.2 C
ONTROL
R
EGISTER
(O
FFSET
14
H
) ..............................................................................................................................15
9.3 S
TATUS
R
EGISTER
(O
FFSET
14
H
)..................................................................................................................................16
9.4 I
NTERRUPT
C
ONTROL
R
EGISTER
(O
FFSET
18
H
)........................................................................................................17
9.5 T
EST
B
US
C
ONTROLLER
-TBC (O
FFSETS
80
H
-AF
H
)...................................................................................................17
10. BRIDGE - C40 OPERATION. .......................................................................................................................................... 19
10.1 8.1. FIFO..........................................................................................................................................................................19
10.2 8.2. PCI A
DDRESS
...........................................................................................................................................................20
10.3 8.3. C40 C
ONT ROL
R
EGISTER
.......................................................................................................................................20
11. PHYSICAL CHARACTERISTICS .................................................................................................................................. 21
11.1 P
OWER
C
ONSUMPTION
................................................................................................................................................21
11.2 B
OARD
D
IMENSIONS
.....................................................................................................................................................21
Figure 1 Motherboard Architecture......................................................................................................6
Figure 2 Patch Area Layout ...............................................................................................................7
Figure 3 Front Panel .........................................................................................................................9
Table 1 Buffered Communication Port ............................................................................................... 10
Table 2 JTAG Slave Port (Input)........................................................................................................ 11
Table 3 JTAG Master Port (Output)................................................................................................... 12
Table 4 FMS Connector................................................................................................................... 13
