S/AI
Hardware Reference
Page 16 of 52
VDDIO
(+1.2V .. +3.6V)
S
GND
D-2
F-4
F-3
D-7
UART_RXD
UART_TXD
UART_CTS#
UART_RTS#
10µ+100n+1n
SN74AVC4T245
User Host System
VSUP
XC6204B-3.3
VOUT
VSS
VIN
CE
1µ
10
0k
100k
VCCB
1B1
1B2
2B1
2B2
2A2
2A1
1A2
1A1
VCCA
1DIR
1OE
2DIR
2OE
(GPIO, Out,
no pu/pd)
(GPIO, Out,
no pu/pd)
TXD
RTS#
RXD
CTS#
+5VDC
OE_DRV#
BT_ENABLE
VDD_HOST (+1.2 .. +3.6V)
+3V3_switched
Figure 6: S Example Serial Interface (Mixed Signal Level)
3.4.2 Baudrate Deviation
The following table shows the deviation in percent of the standard data rates. The deviation may
be caused by the inaccuracy of the crystal oscillator or granularity of the baud rate generator.
Data Rate (bits/s)
Deviation (%)
9600
±1%
19200
38400
57600
115200
230400
460800
921600
1000000
Table 3: Deviation of Baudrates
Note: The total deviation of sender and receiver shall not exceed 2,5% to prevent loss of data.