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Functional overview

STM32F038x6

DocID026079 Rev 3

3.4 Cyclic

redundancy

check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.

3.5 Power

management

3.5.1

Power supply schemes

•

V

DD

= V

DDIO1

= 1.8 V

±

8%: external power supply for I/Os (V

DDIO1

) and digital logic. It

is provided externally through VDD pins.

•

V

DDA

= from V

DD

to 3.6 V: external analog power supply for ADC, RCs and PLL

(minimum voltage to be applied to V

DDA

is 2.4 V when the ADC is used). It is provided

externally through VDDA pin. The V

DDA

voltage level must be always greater or equal

to the V

DD

voltage level and must be established first.

•

V

BAT

= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when V

DD

is not present.

For more details on how to connect power pins, refer to

Figure 11: Power supply scheme

3.5.2 Power-on

reset

To guarantee a proper power-on reset, the NPOR pin must be held low until V

DD

is stable.

When V

DD

is stable, the reset state can be exited either by:

•

putting the NPOR pin in high impedance (NPOR pin has an internal pull-up), or by

•

forcing the pin to high level by connecting it to V

DDA

3.5.3 Low-power

modes

The STM32F038x6 microcontrollers support two low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:

•

Sleep

mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.

•

Stop

mode

Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, RTC, I2C1 or USART1.
USART1 and I2C1 peripherals can be configured to enable the HSI RC oscillator so as
to get clock for processing incoming data.

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Содержание STM32F038C6

Страница 1: ...mer for 6 channels PWM output with deadtime generation and emergency stop 1 x 32 bit and 1 x 16 bit timer with up to 4 IC OC usable for IR control decoding 1 x 16 bit timer with 2 IC OC 1 OCN deadtime...

Страница 2: ...nterrupt controller NVIC 15 3 9 2 Extended interrupt event controller EXTI 15 3 10 Analog to digital converter ADC 15 3 10 1 Temperature sensor 16 3 10 2 Internal voltage reference VREFINT 16 3 10 3 V...

Страница 3: ...rating conditions at power up power down 42 6 3 3 Embedded reference voltage 42 6 3 4 Supply current characteristics 42 6 3 5 Wakeup time from low power mode 52 6 3 6 External clock source characteris...

Страница 4: ...on 80 7 2 UFQFPN32 package information 82 7 3 UFQFPN28 package information 86 7 4 WLCSP25 package information 89 7 5 TSSOP20 package information 92 7 6 Thermal characteristics 95 7 6 1 Reference docum...

Страница 5: ...n from VDD supply at VDD 1 8 V 44 Table 22 Typical and maximum current consumption from the VDDA supply 45 Table 23 Typical and maximum consumption in Stop mode 45 Table 24 Typical and maximum current...

Страница 6: ...56 WWDG min max timeout value at 48 MHz PCLK 74 Table 57 I2C analog filter characteristics 75 Table 58 SPI characteristics 75 Table 59 I2 S characteristics 77 Table 60 LQFP48 package mechanical data 8...

Страница 7: ...nput characteristics 65 Figure 21 I O AC characteristics definition 67 Figure 22 Recommended NRST pin protection 68 Figure 23 ADC accuracy characteristics 72 Figure 24 Typical connection diagram using...

Страница 8: ...ics of the STM32F038x6 microcontrollers This document should be read in conjunction with the STM32F0xxxx reference manual RM0091 The reference manual is available from the STMicroelectronics website w...

Страница 9: ...chosen different sets of peripherals are included These features make the STM32F038x6 microcontrollers suitable for a wide range of applications such as application control and user interfaces hand he...

Страница 10: ...5 57 50 287 9 7 6 6 6 3 9 5B287 DV FKDQQHO FRPSO 5 DV FKDQQHO FRPSO 5 DV FKDQQHO DV FK 75 DV FK 75 DV 3 0 FKDQQHOV 257 0 38 I0 0 6HULDO LUH HEXJ 19 7 7 83 63 6 6 6 0 8 LQGRZ 3 5 5 6 7 2 21752 3 0 7 0...

Страница 11: ...of embedded SRAM accessed read write at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail critical applications The non volatile memory is di...

Страница 12: ...supply for RTC external clock 32 kHz oscillator and backup registers through power switch when VDD is not present For more details on how to connect power pins refer to Figure 11 Power supply scheme...

Страница 13: ...ck can be selected in which case it is monitored for failure If failure is detected the system automatically switches back to the internal RC oscillator A software interrupt is generated if enabled Si...

Страница 14: ...figuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I Os registers 06Y 9 26 B 1 26 B287 26 B 1 26 B287 3 08 0 2 0DLQ FORFN RXWSXW 3 6 6 3 FRUH PH...

Страница 15: ...oupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail chaining Processor state automatically saved Interrupt entry re...

Страница 16: ...e in read only mode 3 10 2 Internal voltage reference VREFINT The internal voltage reference VREFINT provides a stable bandgap voltage output for the ADC VREFINT is internally connected to the ADC_IN1...

Страница 17: ...he counter can be frozen in debug mode Many features are shared with those of the standard timers which have the same architecture The advanced control timer can therefore work together with the other...

Страница 18: ...se mode output Its counter can be frozen in debug mode TIM16 and TIM17 Both timers are based on a 16 bit auto reload upcounter and a 16 bit prescaler They each have a single channel for input capture...

Страница 19: ...om 1 to 32767 RTC clock pulses This can be used to synchronize the RTC with a master clock digital calibration circuit with 1 ppm resolution to compensate for quartz crystal inaccuracy two anti tamper...

Страница 20: ...nication mode USART1 supports also SmartCard communication ISO 7816 IrDA SIR ENDEC LIN Master Slave capability and auto baud rate feature and has a clock domain independent of the CPU clock allowing t...

Страница 21: ...ware flow control for modem X Continuous communication using DMA X Multiprocessor communication X Synchronous mode X Smartcard mode X Single wire half duplex communication X IrDA SIR ENDEC block X LIN...

Страница 22: ...slave at half duplex communication mode It can be configured to transfer 16 and 24 or 32 bits with 16 bit or 32 bit data resolution and synchronized by a specific signal Audio sampling frequency from...

Страница 23: ...nout Figure 4 UFQFPN32 package pinout 06Y 9 3 3 3 3 3 3 3 1325 3 3 966 9 9 7 3 3 26 B 1 3 26 B287 3 26 B 1 3 26 B287 1567 966 9 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 227 3 3 966 9 d 4 3 06Y 9 SR...

Страница 24: ...SP25 package pinout 1 The above figure shows the package in top view changing from bottom view in the previous document versions 06Y 9 3 3 3 3 3 3 3 227 3 26 B 1 3 26 B287 1567 9 3 3 3 3 3 3 9 966 132...

Страница 25: ...DocID026079 Rev 3 25 102 STM32F038x6 Pinouts and pin description 32 Figure 7 TSSOP20 package pinout 06Y 9 3 26 B 1 227 3 26 B287 1567 9 3 3 9 3 3 3 1325 966 3 3 3 3 3 3 3 7RS YLHZ 76623...

Страница 26: ...d from VDDA TC Standard 3 3V I O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull up resistor Notes Unless otherwise specified by a note all I Os are set as floating inputs du...

Страница 27: ...C4 7 PA1 I O TTa TIM2_CH2 EVENTOUT USART1_RTS ADC_IN1 12 8 8 D4 8 PA2 I O TTa TIM2_CH3 USART1_TX ADC_IN2 13 9 9 E5 9 PA3 I O TTa TIM2_CH4 USART1_RX ADC_IN3 14 10 10 B3 10 PA4 I O TTa SPI1_NSS I2S1_WS...

Страница 28: ...O FTf TIM2_CH3 I2C1_SCL 22 PB11 I O FTf TIM2_CH4 EVENTOUT I2C1_SDA 23 0 16 E1 15 VSS S Ground 24 17 17 D1 16 VDD S Digital power supply 25 PB12 I O FT TIM1_BKIN EVENTOUT SPI1_NSS 26 PB13 I O FT TIM1_C...

Страница 29: ...I O FT 5 IR_OUT SWDIO 35 PF6 I O FTf I2C1_SCL 36 PF7 I O FTf I2C1_SDA 37 24 22 A2 20 PA14 SWCLK I O FT 5 USART1_TX SWCLK 38 25 23 PA15 I O FT 6 SPI1_NSS I2S1_WS TIM2_CH_ETR EVENTOUT USART1_RX 39 26 2...

Страница 30: ...power up PC13 PC14 and PC15 operate as GPIOs Their function then depends on the content of the RTC registers which are not reset by the system reset For details on how to manage these GPIOs refer to...

Страница 31: ..._CH4 PA4 SPI1_NSS I2S1_WS USART1_CK TIM14_CH1 PA5 SPI1_SCK I2S1_CK TIM2_CH1_ ETR PA6 SPI1_MISO I2S1_MCK TIM3_CH1 TIM1_BKIN TIM16_CH1 EVENTOUT PA7 SPI1_MOSI I2S1_SD TIM3_CH2 TIM1_CH1N TIM14_CH1 TIM17_C...

Страница 32: ...N PB2 PB3 SPI1_SCK I2S1_CK EVENTOUT TIM2_CH2 PB4 SPI1_MISO I2S1_MCK TIM3_CH1 EVENTOUT PB5 SPI1_MOSI I2S1_SD TIM3_CH2 TIM16_BKIN I2C1_SMBA PB6 USART1_TX I2C1_SCL TIM16_CH1N PB7 USART1_RX I2C1_SDA TIM17...

Страница 33: ...32F038x6 memory map 06 9 3HULSKHUDOV 65 0 ODVK PHPRU 5HVHUYHG 6 VWHP PHPRU 2SWLRQ WHV ODVK V VWHP PHPRU RU 65 0 GHSHQGLQJ RQ 227 FRQILJXUDWLRQ 5HVHUYHG 2 3 3 5HVHUYHG 5HVHUYHG 5HVHUYHG RUWH 0 LQWHUQDO...

Страница 34: ...nterface 0x4002 1400 0x4002 1FFF 3 KB Reserved 0x4002 1000 0x4002 13FF 1 KB RCC 0x4002 0400 0x4002 0FFF 3 KB Reserved 0x4002 0000 0x4002 03FF 1 KB DMA 0x4001 8000 0x4001 FFFF 32 KB Reserved APB 0x4001...

Страница 35: ...00 0x4000 53FF 8KB Reserved 0x4000 3000 0x4000 33FF 1KB IWDG 0x4000 2C00 0x4000 2FFF 1KB WWDG 0x4000 2800 0x4000 2BFF 1KB RTC 0x4000 2400 0x4000 27FF 1KB Reserved 0x4000 2000 0x4000 23FF 1KB TIM14 0x4...

Страница 36: ...to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 6 1 2 Typical values Unless otherwise specified typical data are based on TA 25 C VDD 1 8 V and VD...

Страница 37: ...led with filtering ceramic capacitors as shown above These capacitors must be placed as close as possible to or below the appropriate pins on the underside of the PCB to ensure the good functionality...

Страница 38: ...Electrical characteristics STM32F038x6 38 102 DocID026079 Rev 3 6 1 7 Current consumption measurement Figure 12 Current consumption measurement scheme 06 9 9 7 9 9 B9 7...

Страница 39: ...ain supply voltage 0 3 1 95 V VDDA VSS External analog supply voltage 0 3 4 0 V VDD VDDA Allowed voltage difference for VDD VDDA 0 4 V VBAT VSS External backup supply voltage 0 3 4 0 V VIN 2 2 VIN max...

Страница 40: ...onnected to the external power supply in the permitted range 2 This current consumption must be correctly distributed over all I Os and control pins The total output current must not be sunk sourced b...

Страница 41: ...2 1 BOOT0 0 5 2 PD Power dissipation at TA 85 C for suffix 6 or TA 105 C for suffix 7 2 LQFP48 364 mW UFQFPN32 526 UFQFPN28 169 WLCSP25 267 TSSOP20 182 TA Ambient temperature for the suffix 6 version...

Страница 42: ...ribed in Figure 12 Current consumption measurement scheme Table 19 Operating conditions at power up power down Symbol Parameter Conditions Min Max Unit tVDD VDD rise time rate 0 s V VDD fall time rate...

Страница 43: ...ng conditions All I O pins are in analog input mode All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency 0 wait state and Prefe...

Страница 44: ...current in Run mode code executing from RAM External clock HSE bypass 48 MHz 17 2 18 7 19 1 19 3 10 2 10 6 11 1 11 4 32 MHz 11 4 12 2 12 4 12 7 6 7 7 2 7 4 7 6 24 MHz 8 9 9 4 9 6 9 7 5 1 5 5 5 7 5 7...

Страница 45: ...172 195 203 206 190 210 222 226 24 MHz 150 170 177 180 165 186 193 196 HSI clock PLL off 8 MHz 71 83 87 88 81 95 97 98 1 Current consumption from the VDDA supply is independent of whether the digital...

Страница 46: ...or frequencies greater than 8 MHz AHB prescaler of 2 4 8 and 16 is used for the frequencies 4 MHz 2 MHz 1 MHz and 500 kHz respectively Table 24 Typical and maximum current consumption from the VBAT su...

Страница 47: ...to I Os configured as inputs if an intermediate voltage level is externally applied This current consumption is caused by the input Schmitt Table 25 Typical current consumption code executing from Fl...

Страница 48: ...y using pull up down resistors or by configuring the pins in output mode I O dynamic current consumption In addition to the internal peripheral current consumption measured previously see Table 27 Per...

Страница 49: ...NT CEXT CS 2 MHz 0 09 mA 4 MHz 0 17 8 MHz 0 34 18 MHz 0 79 36 MHz 1 50 48 MHz 2 06 VDDIOx 1 8 V CEXT 10 pF C CINT CEXT CS 2 MHz 0 13 4 MHz 0 26 8 MHz 0 50 18 MHz 1 18 36 MHz 2 27 48 MHz 3 03 VDDIOx 1...

Страница 50: ...cked off with only one peripheral clocked on Ambient operating temperature and supply voltage conditions summarized in Table 15 Voltage characteristics The power consumption of the digital part of the...

Страница 51: ...l APB peripherals 110 9 1 The BusMatrix automatically is active when at least one master is ON CPU or DMA1 2 The APBx Bridge is automatically active when at least one peripheral is ON on the same Bus...

Страница 52: ...Table 18 General operating conditions 6 3 6 External clock source characteristics High speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and...

Страница 53: ...input waveform is shown in Figure 14 Figure 14 Low speed external clock source AC timing diagram Table 30 Low speed external user clock characteristics Symbol Parameter 1 1 Guaranteed by design not t...

Страница 54: ...of CL1 and CL2 PCB and MCU pin capacitance must be included 10 pF can be used as a rough estimate of the combined pin and board capacitance when sizing CL1 and CL2 Note For information on selecting th...

Страница 55: ...tor and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufactu...

Страница 56: ...scillator transconductance LSEDRV 1 0 00 lower driving capability 5 A V LSEDRV 1 0 01 medium low driving capability 8 LSEDRV 1 0 10 medium high driving capability 15 LSEDRV 1 0 11 higher driving capab...

Страница 57: ...nit fHSI Frequency 8 MHz TRIM HSI user trimming step 1 2 2 Guaranteed by design not tested in production DuCy HSI Duty cycle 45 2 55 2 ACCHSI Accuracy of the HSI oscillator TA 40 to 105 C 2 8 3 3 Data...

Страница 58: ...er Conditions Min Typ Max Unit fHSI14 Frequency 14 MHz TRIM HSI14 user trimming step 1 2 2 Guaranteed by design not tested in production DuCy HSI14 Duty cycle 45 2 55 2 ACCHSI14 Accuracy of the HSI14...

Страница 59: ...tup time 85 s IDDA LSI 2 LSI oscillator power consumption 0 75 1 2 A Table 36 PLL characteristics Symbol Parameter Value Unit Min Typ Max fPLL_IN PLL input clock 1 1 Take care to use the appropriate m...

Страница 60: ...d noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance...

Страница 61: ...e are monitored while a simple application is executed toggling 2 LEDs through the I O ports This emission test is compliant with IEC 61967 2 standard which specifies the test board and the pin loadin...

Страница 62: ...current into the I O pins programmed in floating input mode While current is injected into the I O pin one at a time the device is checked for functional failures The failure is indicated by an out of...

Страница 63: ...l FT FTf and POR pins 5 NA Injected current on all TTa TC and RESET pins 5 5 Table 44 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Low level input voltage TC and TTa I O...

Страница 64: ...equivalent resistor 3 VIN VSS 25 40 55 k RPD Weak pull down equivalent resistor 3 VIN VDDIOx 25 40 55 k CIO I O pin capacitance 5 pF 1 Data based on design simulation only Not tested in production 2 T...

Страница 65: ...ics 06Y 9 7 67 5 1 7 67 5 1 9 PLQ 9 2 026 VWDQGDUG UHTXLUHPHQW 9 PD 9 2 026 VWDQGDUG UHTXLUHPHQW 81 1 1387 5 1 9 PLQ 9 2 9 PD 9 2 9 1 9 9 2 9 77 VWDQGDUG UHTXLUHPHQW 77 VWDQGDUG UHTXLUHPHQW 06Y 9 7 67...

Страница 66: ...otherwise specified the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 18 General operating condit...

Страница 67: ...ions Min Max Unit x0 fmax IO out Maximum frequency 3 3 The maximum frequency is defined in Figure 21 CL 50 pF 1 MHz tf IO out Output fall time 125 ns tr IO out Output rise time 125 01 fmax IO out Maxi...

Страница 68: ...NPOR pin input driver uses the CMOS technology It is connected to a permanent pull up resistor to the VDDA RPU Unless otherwise specified the parameters given in Table 48 below are derived from tests...

Страница 69: ...25 40 55 k 1 Guaranteed by design not tested in production 2 The pull up is designed with a true resistance in series with a switchable PMOS This PMOS contribution to the series resistance is minimal...

Страница 70: ...C 14 MHz 0 107 17 1 s 1 5 239 5 1 fADC tSTAB 2 Stabilization time 14 1 fADC tCONV 2 Total conversion time including sampling time fADC 14 MHz 12 bit resolution 1 18 s 12 bit resolution 14 to 252 tS fo...

Страница 71: ...error 1 2 1 7 ET Total unadjusted error fPCLK 48 MHz fADC 14 MHz RAIN 10 k VDDA 2 4 V to 3 6 V TA 25 C 3 3 4 LSB EO Offset error 1 9 2 8 EG Gain error 2 8 3 ED Differential linearity error 0 7 1 3 EL...

Страница 72: ...ure 11 Power supply scheme The 10 nF capacitor should be ceramic good quality and it should be placed as close as possible to the chip 7 7RWDO 8QDMXVWHG UURU PD LPXP GHYLDWLRQ EHWZHHQ WKH DFWXDO DQG L...

Страница 73: ...pling time when reading the temperature 4 s 1 Guaranteed by design not tested in production 2 Measured at VDDA 3 3 V 10 mV The V30 ADC conversion result is stored in the TS_CAL1 byte Refer to Table 3...

Страница 74: ...t current maximum requirement Refer to Section 6 3 13 I O port characteristics for the I2 C I Os characteristics All I2 C SDA and SCL I Os embed an analog filter Refer to the table below for the analo...

Страница 75: ...equency Master mode 18 MHz Slave mode 18 tr SCK tf SCK SPI clock rise and fall time Capacitive load C 15 pF 6 ns tsu NSS NSS setup time Slave mode 4Tpclk ns th NSS NSS hold time Slave mode 2Tpclk 10 t...

Страница 76: ...t points are done at CMOS levels 0 3 VDD and 0 7 VDD DL F 6 QSXW 166 LQSXW W68 166 WF 6 WK 166 3 32 3 32 WZ 6 WZ 6 W9 62 WK 62 WU 6 WI 6 WGLV 62 WD 62 0 62 287387 026 1387 06 287 7 287 6 287 WVX 6 WK...

Страница 77: ...eristics 1 Symbol Parameter Conditions Min Max Unit fCK 1 tc CK I2 S clock frequency Master mode data 16 bits Audio frequency 48 kHz 1 597 1 601 MHz Slave mode 0 6 5 tr CK I2 S clock rise time Capacit...

Страница 78: ...th SD_SR 2 Slave receiver 0 5 tv SD_MT 2 Data output valid time Master transmitter 4 tv SD_ST 2 Slave transmitter 31 th SD_MT Data output hold time Master transmitter 0 th SD_ST Slave transmitter 13...

Страница 79: ...ion results not tested in production 2 LSB transmit receive of the previously transmitted byte No LSB transmit receive is sent before the first byte 06Y 9 RXWSXW 32 32 WF 6 RXWSXW 6 UHFHLYH 6 WUDQVPLW...

Страница 80: ...of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 7 1 LQFP48 p...

Страница 81: ...ts Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 c 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 20...

Страница 82: ...ore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in p...

Страница 83: ...ale 2 All leads pads should also be soldered to the PCB to improve the lead pad solder joint life 3 There is an exposed die pad on the underside of the UFQFPN package This pad is used for the device g...

Страница 84: ...Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 020 0 050 0 0000 0 0008 0 0020 A3 0 152 0 0060 b 0 180 0 230 0 280 0 0071 0 0091 0 0110 D 4 900 5 000 5 100 0 1929 0 1969 0...

Страница 85: ...ng Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be l...

Страница 86: ...ical data 1 Symbol millimeters inches Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 050 0 0000 0 0020 D 3 900 4 000 4 100 0 1535 0 1575 0 1614 D1 2 900 3 000 3 100 0 1142...

Страница 87: ...87 102 STM32F038x6 Package information 98 Figure 37 Recommended footprint for UFQFPN28 package 1 Dimensions are expressed in millimeters 1 Values in inches are converted from mm and rounded to 4 deci...

Страница 88: ...neering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will...

Страница 89: ...ers inches 1 Min Typ Max Min Typ Max A 0 525 0 555 0 585 0 0207 0 0219 0 0230 A1 0 175 0 0069 A2 0 380 0 0150 A3 2 0 025 0 0010 b 3 4 0 220 0 250 0 280 0 0087 0 0098 0 0110 D 2 388 2 423 2 458 0 0940...

Страница 90: ...n is measured at the maximum bump diameter parallel to primary datum Z 4 Primary datum Z and seating plane are defined by the spherical crowns of the bump Table 64 WLCSP25 recommended PCB design rules...

Страница 91: ...y an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no even...

Страница 92: ...ackage mechanical data Symbol millimeters inches 1 Min Typ Max Min Typ Max A 1 200 0 0472 A1 0 050 0 150 0 0020 0 0059 A2 0 800 1 000 1 050 0 0315 0 0394 0 0413 b 0 190 0 300 0 0075 0 0118 c 0 090 0 2...

Страница 93: ...rom mm and rounded to four decimal digits 2 Dimension D does not include mold flash protrusions or gate burrs Mold flash protrusions or gate burrs shall not exceed 0 15mm per side 3 Dimension E1 does...

Страница 94: ...Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liab...

Страница 95: ...d in Watts This is the maximum chip internal power PI O max represents the maximum power dissipation on output pins where PI O max VOL IOL VDDIOx VOH IOH taking into account the actual VOL IOL and VOH...

Страница 96: ...0 I Os used at the same time in output at low level with IOL 8 mA VOL 0 4 V and maximum 8 I Os used at the same time in output at low level with IOL 20 mA VOL 1 3 V PINTmax 50 mA 3 5 V 175 mW PIOmax 2...

Страница 97: ...70 mW PIOmax 20 8 mA 0 4 V 64 mW This gives PINTmax 70 mW and PIOmax 64 mW PDmax 70 64 134 mW Thus PDmax 134 mW Using the values obtained in Table 66 TJmax is calculated as follows For LQFP48 55 C W...

Страница 98: ...formation scheme Example STM32 F 038 G 6 T 6 x Device family STM32 ARM based 32 bit microcontroller Product type F General purpose Sub family 038 STM32F038xx Pin count F 20 pins E 25 pins G 28 pins K...

Страница 99: ...m current consumption from VDD supply at VDD 1 8 V Table 21 Typical and maximum current consumption from the VDDA supply Table 23 Typical and maximum current consumption from the VBAT supply Table 19...

Страница 100: ...ional overview Figure 2 Clock tree updated Section 3 5 3 Low power modes added inf on peripherals configurable to operate with HSI Section 3 10 2 Internal voltage reference VREFINT removed information...

Страница 101: ...3 and 4 Section 6 3 15 12 bit ADC characteristics changed introductory sentence Table 59 I2S characteristics table reorganized tv SD_ST max value updated Section 7 Package information Figure 37 Recom...

Страница 102: ...rchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implie...

Страница 103: ...r Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information STMicroelectronics STM32F038F6P6 STM32F038K6U6 STM32F038C6T6 STM32F038C6T7 STM32F038G6U6 STM32F038E6...

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