Step Technica MKY02, Руководство пользователя

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Chapter 4 Cascade Connection of MKY02
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4.2.3 Connection of Cascade Clocks and Determination of Baud Rate
The MKY02 has a circuit which generates a cascade clock. A cascade clock for a baud rate suitable for the
settings of the BPS1 and BPS0 pins from the clock to be input to the Xi pin (refer to
“3.2.2 Setting Cas-
cade Clock and Baud Rate” ).
When multiple MKY02s are is cascade-connected for use, the cascade clock generated by the highest-prior-
ity MKY02 is supplied to another MKY02 (Fig. 4.7). The baud rate set for the highest-priority MKY02 also
applies to another MKY02.
Handle any MKY02 other than the highest-priority one as follows (refer to Fig. 4.7):
(1) Fix the Xi pin (pin 34) at a Low level or a High level (when left open, this pin can be fixed at a High
level due to an internal pull-up resistor).
(2) Fix the BPS0 pin (pin 52) and BPS1 (pin 53) pin at a Low level or a High level (when left open, these
pins can be fixed at a High level due to an internal pull-up resistor).
(3) Leave the AXS0 pin (pin 36), AXS1 pin (pin 40), and AXS2 pin (pin 42) pin open.
In-phase clocks must be supplied to the AX0, AX1, and AX2 pins of all MKY02s to be
cascade-connected. Therefore, when connecting cascade clocks, equalize the circuit pat-
tern length of three clock lines. The circuit pattern length must be within 40 cm.
4.2.4 Connection of Hardware Reset Signal
Connect the hardware reset signal common to all MKY02s to be cascade-connected to the #RST pin (pin 35)
(Fig. 4.7). For the specification of the hardware reset signal, follow the description in
“3.2.3 Hardware
Reset”
.