Stanford Research Systems SR844, Руководство пользователя

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Circuit Descriptions 6-11
SR844 RF Lock-In Amplifier
Interconnects
Cable connections on the motherboard are shown on page MBDMAIN, while the dual-
in-line interconnects to daughter boards are shown separately on successive pages.
MPLAT: Platform Interface
The address ( BA0–BA4 ), data ( BD0–BD7 ) and control ( BC2–BC6 ) lines from the ‘186
host processor come from the CPU/Power Supply board 844C on connector J3. U800
buffers the data lines, while U801 and U804A buffer the address lines. The address lines
(and data lines, actually) are gated by
-PCS4
port select strobe on 844C, so gating of
U801 is not necessary. The addresses are decoded by U802 (read strobe) and U803
(write strobe). Some of these decoded-address strobes are used to select registers while
others are used for clear, load and clock pulses directly.
The two input (read) latches are U808, which reads the range bits determined in the
Range Select section, and U809, which reads the various status (error, overload) bits.
Most of the inputs and the data bus are accessible on test points that are labelled on the
board.
There are four output (write) registers. U807 is a latch that writes range select and loop
filter bits to the Range Select section in internal reference mode. U810–812 are the
registers that set the control bits for all the various boards. The signal control bits are in
U810, the I.F. control bits are in U812, and the rest of the control bits are distributed
among the registers. The digital outputs go through resistors for isolation. Many output
bits have test points either on the motherboard or at their destination on another board.
Programmable chip U813 latches the various status bits, so that a transient error can be
caught and read by the host ‘186.
MSYNT: Synthesizer
U821 is a 20MHz crystal TTL oscillator. Its output is gated by U822B and used as the
reference for the synthesizer chip U820. This chip divides the reference input and the
F
input by different integers and generates error pulses on pins
R
and
V
(the signals are
INTUP
and
INTDN
) if the edges of the divided-down signals don’t match up precisely.
These signals are used as feedback in a phase-locked loop so as to lock the
F
input to the
20 MHz reference. The actual frequency of
F
depends on the divisors programmed into
the synthesizer chip. The
F
input lines come from the VCO on 84XRF, they are
terminated by R820 and AC coupled into the synthesizer. The programming inputs
SY0–SY2
come from the Platform interface above. The outputs
INTUP
and
INTDN
go
to the Loop Filter on 84XRF. An auxiliary output
-INT.LOCK
is returned to the
Platform Interface after filtering; this signal goes low when the synthesizer is not phase-
locked.
The 20 MHz clock signal from U821 is buffered by U822A and attenuated by
R823/C823. This signal is sent to 84DSP for use as the DSP clock.