Hardware and layout
UM1574
18/48
Doc ID 023645 Rev 1
Figure 10.
STM8AF5288T block diagram
MS31062V1
XTAL 1-24 MHz
RC int. 16 MHz
RC int. 128 kHz
STM8A CORE
Debug/SWIM
I
2
C
SPI
USART
LINUART
16-bit general purpose
AWU timer
Reset block
Reset
Clock controller
Detector
Clock to peripherals and core
10
Mbit/s
LIN master
Up to
Window WDG
IWDG
Up to 128 Kbyte
Up to 2 Kbytes
Up to 6 Kbytes
Boot ROM
10-bit ADC
beCAN
9 CAPCOM
Reset
400 Kbit/s
1 Mbit/s
Master/slave
Single wire
automatic
debug interf.
SPI emul.
channels
high density program
Flash
16-bit advanced control
timer (TIM1)
(TIM2, TIM3)
8-bit AR timer
(TIM4)
data EEPROM
RAM
Up to
Ad
dress
and
da
ta b
u
s
16 channels
resynchronization
POR
BOR