Hardware layout and configuration
UM1902
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DocID027916 Rev 2
All signals for memory are also connected on memory connectors CN10 and CN11 for
memory daughterboards.
Some limitation can happen when using other peripherals:
1.
FMC addressing limitation depending number of Trace data bus used (A18 max for 4
bit ETM to A21 max for 1 bit ETM)
2. FMC addresses limited to A21 when SAI used
3. FMC addresses limited to A20 when Camera is used
4. FMC addresses limited to A22 when Ethernet is used
In such cases, memory addresses A19 to A22 not connected to FMC, are pulled down, so
that memories can be addressed within a limited address range. If A21 or A22 is required,
the camera board should be removed on the board.
5.15
Quad-SPI Nor Flash memory
512-Mbit Quad-SPI Nor Flash memory is connected to Quad-SPI interface of the
STM32F746NGH6 microcontroller on STM32746G-EVAL evaluation board.
5.16 Analog
input
The two-pin header CN3 and 10K ohm potentiometer RV1 are connected to PF10 of the
STM32F746NGH6 microcontroller as analog input. A low pass filter can be implemented by
replacing of R29 and C24 with right value of resistor and capacitor, as requested by the end
user application.
PF10 is shared with LED1 and can be set by jumper JP24. Refer to
for details.
5.17 Camera
module
A connector CN4 for DCMI signals is on STM32746G-EVAL evaluation board and camera
module daughterboard MB1183.
DCMI signals are duplicated with other peripherals (SAI, I2S, Nor Flash memory, microSD
card, TRACE, MEMS Microphone and LED3).
These peripherals may not function correctly if camera module is being used. VSYNC signal
is shared with LED3 and can be set by jumper JP23. Refer to
for details.
Table 12. NOR Flash memory related jumpers
Jumper
Description
JP10
Write protection is enabled when JP10 is fitted while write protection is disabled
when JP10 is not fitted.
Default setting: Not fitted
JP5
Description of JP5 is in
