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UM1935
Hardware Layout and configuration
76
5.14 Memories
8M x 32bit SDRAM is connected to the bank 1 of the SDRAM of FMC interface of
STM32F479NIH6.
1Mx16bit SRAM is connected to the bank1 of the NOR/PSRAM2 of FMC interface and both
8bit and 16bit access are allowed by BLN0 and BLN1 connected to BLE and BHE of SRAM
respectively.
128Mbit NOR Flash is connected to the bank1 of the NOR/PSRAM1 of FMC interface. The
16bit operation mode is selected by pull-up resistor connected to BYTE pin of NOR Flash.
The write protection can be enabled or disabled depending on setting of jumper JP11.
All signals for memory are also connected on memory connectors CN10 and CN11 for
memory daughterboards.
Some limitations happen when using other peripherals:
FMC addressing limitation depending on the number of ETM data signals used (A18
max for 4 bit ETM to A21 max for 1 bit ETM).
FMC addresses limited to A18 when SAI is used.
FMC addresses limited to A20 when Camera is used.
FMC addresses limited to A22 when Ethernet is used.
In such cases, serial resistors R37(A19), R35(A20), R32(A21) and R34(A22) should be
removed. Thus memory addresses A19 to A22 are not connected to FMC and they are
pulled down on the board.
Table 11. Ethernet related solder bridges
Solder
bridges
Description
SB48
MII CRS on DP83848CVV is connected to PA0 when SB48 is closed and SB44,
SB46 are open
Default setting: Open
SB63
MII COL on DP83848CVV is connected to PH3 when SB63 is closed and unmount
R243
Default setting: Open
SB12
MII_RX_ER on DP83848CVV is connected to PI10 when SB12 is closed and
unmount R244
Default setting: Open
Table 12. NOR Flash related jumpers
Jumper
Description
JP11
Write protection is enabled when JP11 is fitted while write protection is disabled
when JP11 is not fitted.
Default Setting: Not fitted
JP6
Description of JP6 is in
Section 5.6: Audio
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