Hardware layout and configuration
UM1460
18/67
DocID022136 Rev 5
2.16 Ethernet
The STM3241G-EVAL evaluation board enables 10/100M Ethernet communication by a
PHY DP83848CVV (U5) and integrated RJ45 connector (CN7). Both MII and RMII interface
modes can be selected by setting jumpers JP5, JP6 and JP8 as listed in
Table 12
:
Note:
1
A test point (TP2) is available on the board for the PTP_PPS feature test.
2
The Ethernet PHY (U5) can be powered down by regulating PB14.
3
In RMII mode the 50 MHz clock must be provided to Ethernet PHY by an external oscillator.
This oscillator (ref SM7745HEV-50.0M or equivalent, not provided with the board) must be
soldered on the U3 footprint (located under CN3) and JP5 must be removed.
Table 12. Ethernet related jumpers and solder bridges
Jumper
Description
JP8
JP8 selects MII or RMII interface mode. To enable RMII interface mode, JP8 is fitted.
To enable MII, JP8 is not fitted. Default setting: Not fitted
JP6
To enable MII interface mode, set JP6 as shown (Default setting):
To enable RMII interface mode, set JP6 as shown:
JP5
To provide 25 MHz clock for MII or 50 MHz clock for RMII by MCO at PA8, set
JP5 as shown (Default setting):
To provide 25 MHz clock by external crystal X1 (for MII interface mode only) set
JP5 as shown:
When clock is provided by external oscillator U3, JP5 must not be fitted.
SB1
SB1 selects clock source only for RMII mode.
To connect the clock from oscillator U3 to RMII_REF_CLK, close SB1.
The resistor R212 has to be removed in this case.
Default setting: Closed.
3
2
1
3
2
1
3
2
1
3
2
1
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