Figure 30.
STEVAL-ETH001V1 circuit schematic (7 of 10)
ST
RI
PL
IN
E
AV
AI
LA
BL
E
CONSOLE MODE
1v2
1v2
1v2
1v2
3v3
3v3
3v3
3v3
3v3
3v3
3v3
1v2
U0_CTS
U0_RTS
MLED0/TRACE_DATA_0
MLED1/TRACE_DATA_1
PHY0_TXP
PHY0_TXN
PHY0_RXP
PHY0_RXN
PHY1_TXP
PHY1_TXN
PHY1_RXP
PHY1_RXN
ENDAT0_IN/BISS0_SL
ENDAT0_OUT/BISS0_MO
ENDAT0_OE/BISS0_OE
ENDAT0_CLK/BISS0_MA
MMIO04/ADC0-0
MMIO05/ADC0-1
MMIO06/ADC1-0
MMIO07/ADC1-1
UART_RX
UART_TX
ETH_JT_TMS/SWDIO
ETH_JT_TCK/SWDCLK
ETH_nRST
S
P
I_
M
IS
O
S
P
I_
M
O
S
I
S
P
I_
C
S
n
S
P
I_
C
LK
ETH_JT_TDI
ETH_JT_TDO
MLED2/TRACE_DATA_2
MLED3/TRACE_DATA_3
NETX_RESET
D
P
M
0_
S
P
I_
D
IR
Q
D
P
M
1_
S
P
I_
D
IR
Q
MII
ETH
LED
DC-DC
MMIO
DPM
FLASH
DEBUG
SYSTEM
U10
NETX90
V
S
S
_A
1
A
1
V
D
D
IO
_A
2
A
2
H
IF
_A
8
A
3
H
IF
_A
5
A
4
H
IF
_A
2
A
5
H
IF
_D
15
A
6
H
IF
_D
12
A
7
H
IF
_D
9
A
8
H
IF
_D
6
A
9
H
IF
_D
3
A
10
V
D
D
IO
_A
11
A
11
V
S
S
_A
12
A
12
V
D
D
C
_B
1
B
1
H
IF
_A
10
B
2
H
IF
_A
7
B
3
H
IF
_A
4
B
4
H
IF
_A
1
B
5
H
IF
_D
14
B
6
H
IF
_D
11
B
7
H
IF
_D
8
B
8
H
IF
_D
5
B
9
H
IF
_D
2
B
10
H
IF
_D
0
B
11
VDDC_B12
B12
H
IF
_A
11
C
1
H
IF
_A
9
C
2
H
IF
_A
6
C
3
H
IF
_A
3
C
4
H
IF
_A
0
C
5
H
IF
_D
13
C
6
H
IF
_D
10
C
7
H
IF
_D
7
C
8
H
IF
_D
4
C
9
H
IF
_D
1
C
10
JT_TDI
C11
JT_TDO
C12
H
IF
_A
12
D
1
H
IF
_A
13
D
2
H
IF
_A
14
D
3
H
IF
_A
15
D
4
H
IF
_A
16
D
5
H
IF
_A
17
D
6
H
IF
_B
H
E
N
D
7
H
IF
_C
S
N
D
8
M
II1
_R
X
C
LK
D
9
JT_TRST
D10
JT_TMS
D11
JT_TCK
D12
H
IF
_W
R
N
E
1
H
IF
_R
D
N
E
2
H
IF
_R
D
Y
E
3
M
II0
_C
R
S
E
4
M
II0
_C
O
L
E
5
P
H
Y
1_
LE
D
_L
IN
K
_I
N
E
6
P
H
Y
0_
LE
D
_L
IN
K
_I
N
E
7
M
II1
_C
O
L
E
8
M
II1
_C
R
S
E
9
M
II1
_R
X
E
R
E
10
PHY1_TXN
E11
PHY1_TXP
E12
H
F
I_
S
D
C
LK
F
1
H
F
I_
D
IR
Q
F
2
M
II0
_R
X
E
R
F
3
M
II0
_R
X
C
LK
F
4
M
II0
_T
X
E
N
F
5
VSS_F6
F6
VSS_F7
F7
M
II1
_R
X
D
3/
LV
D
S
1_
R
X
N
F
8
M
II1
_R
X
D
2/
LV
D
S
1_
R
X
P
F
9
M
II1
_R
X
D
V
F
10
PHY1_RXN
F11
PHY1_RXP
F12
SQI_CS0N
G1
SQI_MISO
G2
SQI_SIO2
G3
M
II0
_R
X
D
V
G
4
M
II0
_T
X
C
LK
G
5
VSS_G6
G6
VSS_G7
G7
M
II1
_R
X
D
1/
LV
D
S
1_
T
X
P
G
8
M
II1
_R
X
D
0/
LV
D
S
1_
T
X
N
G
9
UART_RXD
G10
UART_TXD
G11
PHY_EXTRES
G12
SQI_MOSI
H1
SQI_CLK
H2
SQI_SIO3
H3
M
II0
_R
X
D
3
H
4
M
II0
_R
X
D
2
H
5
M
II0
_T
X
D
3
/ A
D
C
3_
IN
5
H
6
M
II0
_T
X
D
2
/ A
D
C
2_
IN
4
H
7
M
II1
_T
X
D
3
/ L
V
D
S
0_
T
X
P
H
8
M
II1
_T
X
D
2
/ L
V
D
S
0_
T
X
N
H
9
M
II1
_T
X
C
LK
/
A
D
C
2_
IN
2
H
10
PHY0_RXN
H11
PHY0_RXP
H12
R
D
Y
_N
J1
R
U
N
_N
J2
B
O
D
J3
M
II0
_R
X
D
1
J4
M
II0
_R
X
D
0
J5
M
II0
_T
X
D
1
/ A
D
C
3_
IN
4
J6
M
II0
_T
X
D
0
/ A
D
C
2_
IN
7
J7
M
II1
_T
X
D
1
/ L
V
D
S
0_
R
X
P
J8
M
II1
_T
X
D
0
/ L
V
D
S
0_
R
X
N
J9
MLED2
J10
PHY0_TXN
J11
PHY0_TXP
J12
PHY0_VDDC
K12
MLED3
K11
MLED1
K10
M
II1
_T
X
E
N
/
A
D
C
2_
IN
3
K
9
M
II_
M
D
C
/
A
D
C
2_
IN
5
K
8
COM_IO0 / ADC3_IN2
K7
COM_IO1 / ADC3_IN3
K6
COM_IO2 / ADC3_IN6
K5
COM_IO3 / ADC3_IN7
K4
VSS_K3
K3
VSS_DCDC(GND)
K2
DCDC_LX_OUT
K1
VDDIO_L1
L1
V
R
E
F
_A
D
C
L2
R
S
T
_O
U
T
_N
L3
MMIO7 / ADC1_IN1
L4
MMIO5 / ADC0_IN7
L5
MMIO3 / ADC3_IN1
L6
MMIO1/ ADC2_IN1
L7
M
II_
M
D
IO
/ A
D
C
2_
IN
6
L8
C
LK
25
O
U
T
L9
MLED0
L10
PHY_VDDIO
L11
VDDIO_L12
L12
V
S
S
_M
12
M
12
VDDC_M11
M11
O
S
C
_X
T
O
(X
T
A
LO
U
T
)
M
10
O
S
C
_X
T
I(
X
T
A
LI
N
)
M
9
VDD_PLL
M8
MMIO0 / ADC2_IN0
M7
MMIO2 / ADC3_IN0
M6
MMIO4 / ADC0_IN0
M5
MMIO6 / ADC1_IN0
M4
R
S
T
_I
N
_N
M
3
V
D
D
C
_M
2
M
2
V
S
S
_R
E
F
M
1
R87
270
L2
10uH
1
2
Y2
25MHz
2
4
3
1
L4
600ohm@100MHz
1
2
C83
100nF
R111
2.7k
D10
LED YELLOW
A
C
C64
100nF
R89
4.7k
R88
270
C63
100nF
C82
100nF
C69
100nF
R92
10k
R91
0R
N.M.
L3
600ohm@100MHz
1
2
C68
10uF
C72
100nF
C81
10uF
J5
con2-strip-male
1
2
C78
100nF
C80
100nF
C73
100nF
D11
LED GREEN
A
C
C70
10uF
C74
100nF
C71
0.1uF
C66
100nF
C77
10uF
C76
10uF
C67
10uF
C61
4pF
C65
100nF
SW1
1437566-3
C62
4pF
J6
con2-strip-male
1
2
C75
100nF
R90
6.49k
C79
10uF
VDDC_1v2
GND
G
N
D
V
D
D
IO
V
D
D
IO
V
D
D
C
_1
v2
INTPHY_VDDC
INTPHY_VDDIO
G
N
D
_R
E
F
G
N
D
G
N
D
GND
GND
X
M
0_
R
X
S
D
_D
07
X
M
0_
IO
1
S
D
_D
01
S
D
_D
03
S
D
_D
05
X
M
0_
IO
0
S
D
_D
00
S
D
_D
04
S
D
_D
06
G
N
D
_R
E
F
S
D
_D
02
X
M
0_
T
X
O
S
C
_X
T
O
O
S
C
_X
T
I
GND
GND
GND
R
D
Y
R
U
N
N
E
T
X
_R
E
S
E
T
R
E
S
E
T
_O
U
T
C
LK
25
UART_RX
UART_TX
GND_REF
GND
3v
3_
B
O
D
NETX_RESET
V
D
D
C
_1
v2
RDY
GND
RUN
GND
GND
INTPHY_VDDC
VDDIO
OSC_XTO
OSC_XTI
INTPHY_VDDIO
BOOT MODE
UM2807
-
Rev 1
page
24
/40
UM2807
Schematic diagrams