ST EVALSTGAP2S Скачать руководство пользователя страница 7

1.3

Drivers logic input signals

Drivers logic input signals can be applied through the dedicated pins of J9 or J10 connector (refer to 

Table 1

 for

details).
It is possible to reduce the required driving signals exploiting the onboard jumpers according to 

Table 6

.

Table 6. 

Input signals settings

Input configuration

Description

Jumper

Default condition

IN+_H = IN-_L

The same input signal is
applied to IN+ of high-side
driver U2 and IN- of low-side
driver U1

JP5

Closed

IN+_L = IN-_H

The same input signal is
applied to IN- of high-side
driver U2 and IN+ of low-side
driver U1

JP6

Closed

IN-_L = IN-_H

The same input signal is
applied to IN- of high-side
driver U2 and IN- of low-side
driver U1

JP7

Open

1.4

Drivers gate resistors

The gate resistors are selected based on the selected power switch and application topology.
It is possible to evaluate different gate drivers of the STGAP2S family by setting few jumpers according to 

Table 7

.

Table 7. 

Gate driver resistors and jumper settings

Gate driver

Feature

JP8, JP10

JP9, JP11

Turn-on resistor

Turn-off resistor

STGAP2SM 

(1)

Separated outputs

Open

Closed

R5, R1

R4, R2

STGAP2SCM 

(2)

Miller Clamp

Closed

Open

R5, R1

R5 // R4

R1 // R2

 

1. •

The presence of D4 and D5 does not influence turn-off speed and these diodes are not required in the final
application. D4 and D5 are mounted on board to speed-up evaluation of STGAP2SC (Miller Clamp version).

2. •

R4, D4, R2 and D5 are only required if differentiated turn-on and turn-off speed are required by the user.

 

1.5

Power stage decoupling

As for all switching applications, high voltage supply is properly decoupled and appropriate decoupling capacitor
is connected to the board to reduce bus ringing and power switch overvoltage spikes during operation.
The board is equipped with a small 1.25 kV DC rated film capacitor (C2) in a convenient position to operate
more safely the power switches. Depending on the application, bus decoupling can be modified also by using the
provided footprint and holes for the bus capacitors C1, C2, C34, C35, C36.

IMPORTANT NOTE: DANGER OF DEATH!
High voltage present on the board! Before operating on the board, ensure that all capacitors are
discharged.

UM2754

Drivers logic input signals

UM2754

 - 

Rev 1

page 7/12

Содержание EVALSTGAP2S

Страница 1: ...values of relevant external components in order to facilitate driver s performance evaluation under different applicative conditions and fine pre tuning of the final application s components Figure 1...

Страница 2: ...SO 8 package so it is possible to evaluate the part number of interest just by replacing the gate driver Figure 2 shows the position of the main components and connectors on the board Figure 2 Main co...

Страница 3: ...ve high 2 IN _H High side driver logic input active low 3 IN _L Low side driver logic input active high 4 IN _L Low side driver logic input active low 5 GND Logic ground 6 VDD Logic supply voltage 7 A...

Страница 4: ...OFF pin to turn off gate path Closed in EVALSTGAP2SM Open in EVALSTGAP2SCM JP12 LS gate voltage configuration selection of negative voltage refer to Table 5 Closed JP13 LS gate voltage configuration d...

Страница 5: ...e 4 also to avoid regulator components damage Table 3 Logic supply voltage selection VDD VDD JP22 Note 3 3 V onboard default 2 3 closed VDD generated from VAUX with Zener diode D2 3 3 V external Open...

Страница 6: ...voltage configuration positive negative Gate driving voltage JP1 JP12 JP17 JP18 Most suited for 15 V 0 V default Closed Closed MOSFET IGBT 15 V 2 7 V Open Closed MOSFET IGBT 19 V 0 V Closed Open SiC 1...

Страница 7: ...P8 JP10 JP9 JP11 Turn on resistor Turn off resistor STGAP2SM 1 Separated outputs Open Closed R5 R1 R4 R2 STGAP2SCM 2 Miller Clamp Closed Open R5 R1 R5 R4 R1 R2 1 The presence of D4 and D5 does not inf...

Страница 8: ...Revision history Table 8 Document revision history Date Version Changes 29 Oct 2020 1 Initial release UM2754 UM2754 Rev 1 page 8 12...

Страница 9: ...configuration 2 1 1 Logic supply voltage VDD 5 1 2 Gate driver supply voltage VH 6 1 3 Drivers logic input signals 7 1 4 Drivers gate resistors 7 1 5 Power stage decoupling 7 Revision history 8 UM2754...

Страница 10: ...tion VDD 5 Table 4 R17 value selection with a 3 3 V Zener diode D2 regulator 5 Table 5 Gate driving voltage configuration positive negative 6 Table 6 Input signals settings 7 Table 7 Gate driver resis...

Страница 11: ...List of figures Figure 1 EVALSTGAP2S demonstration board 1 Figure 2 Main components and connectors position 2 UM2754 List of figures UM2754 Rev 1 page 11 12...

Страница 12: ...ts and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST pro...

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