ST EVALSTGAP2S, Руководство пользователя, Страница: 4 / 12

Table 2. Board jumpers setting
Jumper Permitted configurations Default condition
JP1
HS gate voltage configuration: selection of negative
voltage (refer to
Table 5 )
Closed
JP5 Input signals configuration: IN-_L connected to IN+_H Closed
JP6 Input signals configuration: IN+_L connected to IN-_H Closed
JP7 Input signals configuration: IN-_L connected to IN-_H Open
JP8
HS gate resistor configuration: connection of CLAMP
pin to power gate
Open in EVALSTGAP2SM
Closed in EVALSTGAP2SCM
JP9
HS gate resistor configuration: connection of GOFF pin
to turn-off gate path
Closed in EVALSTGAP2SM
Open in EVALSTGAP2SCM
JP10
LS gate resistor configuration: connection of CLAMP
pin to power gate
Open in EVALSTGAP2SM
Closed in EVALSTGAP2SCM
JP11
LS gate resistor configuration: connection of GOFF pin
to turn-off gate path
Closed in EVALSTGAP2SM
Open in EVALSTGAP2SCM
JP12
LS gate voltage configuration: selection of negative
voltage (refer to
Table 5 )
Closed
JP13
LS gate voltage configuration: direct connection of
DCDCL+ to VH_L net
Open
JP14
HS gate voltage configuration: connection of DCDCH
0V output reference to OUT net
Open
JP15
HS gate voltage configuration: connection of DCDCH-
to GNDISO_H net
Closed
JP16
HS gate voltage configuration: direct connection of
DCDCH+ to VH_H net
Open
JP17
HS gate voltage configuration: selection of positive
voltage (refer to
Table 5 )
Closed
JP18
LS gate voltage configuration: selection of positive
voltage (refer to
Table 5 )
Closed
JP20
LS gate voltage configuration: connection of DCDCL-
to GNDISO_L net
Closed
JP21
LS gate voltage configuration: connection of DCDCL
0V output reference to GNDPWR net
Open
JP22 VDD logic supply configuration (refer to Table 3 ) Closed 2-3
UM2754
Board description and configuration
UM2754 - Rev 1
page 4/12