PCI.412 manual
31.03.2004
Page 24 of 26
Samplerate register
Sets the samplerate for recording.
register name
reg no.
r/w
SPC_SAMPLERATE
20000
w
Samplerate between 157 kHz and 40 MHz (10 MHz for the 10 MHz Version)
The value is a 32 bit integer in the range from 40 MHz down to 157 kHz using an 8 bit divider.
Version
y
1
y
2
y
3
y
4
y
5
...
y
254
y
255
40 MHz
40 MHz
20 MHz
13,33 MHz
10 MHz
8 MHz
...
157,5 kHz.
156,8 kHz
10 MHz
-
-
-
10 MHz
8 MHz
...
157,5 kHz.
156,8 kHz
Data can be read after the board has stopped. The data can be random accessed in blocks of variable length. The trigger event is found
at the position memsize - posttrigger.
W
1k Pretrigger
1k Posttrigger
2k Memsize
Triggerevent
1. value
Example: 2k memsize, 1k
postttrigger
Example: 2k memsize, 3k
postttrigger
3k Posttrigger
2k Memsize
Triggerevent (invisible)
1. value
W
Data format
Data will be read out in 2th complement. Normally the upper 4 bit (bit 12 ...bit 15) will be signed expanded in hardware. With this
feature it is possible to use the read data directly as signed 16 bit integer values.
If the register SPC_PATTERNENABLE is set, the digital inputs will be read out in the upper four bits of the four channels. In this case it is
necessary to divide the data in the analogue and the digital channels before processing the data.
TM_GATELOW or TM_GATEHIGH
SPC_PATTERNENABLE = 0
SPC_PATTERNENABLE = 1
SPC_PATTERNENABLE = 1
bit
channel x (x = 0, 1, 2, 3)
channel x (x = 0, 1, 2, 3)
0
AD 0 (LSB)
AD 0 (LSB)
AD 0 (LSB)
1
AD 1
AD 1
AD 1
2
AD 2
AD 2
AD 2
3
AD 3
AD 3
AD 3
4
AD 4
AD 4
AD 4
5
AD 5
AD 5
AD 5
6
AD 6
AD 6
AD 6
7
AD 7
AD 7
AD 7
8
AD 8
AD 8
AD 8
9
AD 9
AD 9
AD 9
10
AD 10
AD 10
AD 10
11
AD 11 (MSB)
AD 11 (MSB)
AD 11 (MSB)
12
AD 11
channel x Digital 0
channel x Digital 0
13
AD 11
channel x Digital 1
channel x Digital 1
14
AD 11
channel x Digital 2
channel x Digital 2
15
AD 11
channel x Digital 3
1 for the first sample after the gate is
opened otherwise 0