PCI.412 manual
31.03.2004
Page 13 of 26
Block diagram PCI.412
Technical data
Resolution
12 bit
Input range
r
500 mV
r
1 V
r
2 V
Samplerate
160 kHz up to 10 MHz / 40 MHz
Offset error
d
5 LSB
d
4 LSB
d
3 LSB
Bandwidth DC 3 dB
0 Hz to 14 MHz / 21 MHz
Gain error
d
2 %
d
1.5 %
d
1.0 %
Bandwidth AC 3 dB
20 Hz to 14 MHz / 21 MHz
Noise
d
3 LSB
d
3 LSB
d
3 LSB
Differential linearity error
±0.5 LSB typ. (ADC)
Crosstalk
-60 dB
-63 dB
-66 dB
Integral linearity error
r
2 LSB typ. (ADC)
SFDR fs = 1 MHz fck = 40 MHz
69 dBFS typ. (ADC)
ENOB fs = 1 MHz, fck=40 MHz
10.8 bit typ. (ADC)
Dimension
312 mm x 109 mm
ENOB fs=10 MHz, fck=40 MHz
10.8 bit typ. (ADC)
Connector
3 mm BNC female
Aperture jitter
1.2 ps rms (ADC)
Input impedance
50 Ohm or 1 MOhm || 15 pF
Multi: Trigger to 1
st
sample delay
0 to 4 samples (fix)
Overvoltage protection
r
20 V
Multi: Recovery time
d
3 samples
Warm up time
10 minutes
Trigger output delay
6 to 14 samples (fix)
Operating temperatur
0
q
C - 50
q
C
Trigger accuracy
1 sample
Storage temperatur
-10
q
C - 70
q
C
Digital input to analog input delay
1 to 8 samples (fix)
Humidity
10% to 90% non condensing
Ext. clock: output delay
5.5 ns
Ext. clock: delay to internal clock
10 ns
+3.3 V
+5 V
+12 V
-12 V
Sync: board to board trigger jitter
0 samples
Power comsumption (A)
0 mA
2650 mA
35 mA
0 mA
Sync: board to board clock delay
d
1.5 ns
Power consumption (W)
0.0 W
13.3 W
0.4 W
0.0 W