SOYO SY-6VBA 133, Руководство пользователя

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Motherboard Description SY-6VBA 133
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1-8.3 ECC Memory
ECC memory detects multiple-bit errors and corrects single-bit errors.
When ECC memory is installed, the BIOS supports both ECC and non-
ECC mode. ECC mode is enabled in the Setup program. The BIOS
automatically detects if ECC memory is installed and provides the Setup
option for selecting ECC mode. If any non-ECC memory is installed, the
Setup option for ECC configuration does not appear and ECC operation is
not available.
1-9 CHIPSET
The Apollo Pro 133 is a high performance, cost-effective and energy
efficient chip set for the implementation of AGP/PCI/ISA desktop
personal computer systems from 66MHz, 100MHz and 133MHz based on
64-bit Slot 1 super-scalar processors.
The Apollo Pro133 chip set consists of the VT82C693A system controller
(492 pin BGA) and the VT82C596B PCI to ISA bridge (324 pin BGA).
The system controller provides superior performance between the CPU,
DRAM, AGP bus, and PCI bus with pipelined, burst, and concurrent
operation.
The VT82C693A supports eight banks of DRAMs up to 1.5GB. The
DRAM controller supports standard Fast Page Mode (FPM) DRAM,
EDO-DRAM, Synchronous DRAM (SDRAM) and Virtual Channel
SDRAM (VC SDRAM), in a flexible mix / match manner. The
Synchronous DRAM interface allows zero wait state bursting between the
DRAM and the data buffers at 66/100/133 MHz. The eight banks of
DRAM can be composed of an arbitrary mixture of
1M/2M/4M/8M/16M/32MxN DRAMs. The DRAM controller also
supports optional ECC (single-bit error correction and multi-bit detection)
or EC (error checking) capability separately selectable on a bank-by-bank
basis. The DRAM controller can run at either the host CPU bus frequency
(66/100/133 MHz) or at the AGP bus frequency (66 MHz) with built-in
PLL timing control.