Sony TVP-08, Руководство по обучению

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Video Processor
Overview
The purpose of IC511 Video Processor is to combine all of the signals
that need to be displayed and output them to the C boards as R, G and B
signals. In addition, it outputs the sync signals for the deflection circuits,
outputs the Velocity Modulation signal and controls the Automatic Cath-
ode Bias, which is responsible for IK blanking.
Video Processing
Video Inputs
Four different sets of video signals are input to IC511 Video Processor.
Two that can be used for the main video are the Y, U and V signals output
from the DRC and MID boards. The MID signals are output from MID
board to CN513/20, 19 and 18 into IC511/64, 63 and 62. The DRC sig-
nals are output from the DRC board to CN511/2, 4 and 6 into IC511/69, 68
and 67. In addition to these signals a YM/YS signal is output from the
MID board to CN513/15, and then input to an OR circuit consisting of
Q530 and Q546. The other input to the OR circuit comes from IC1008/61
O Sync Sel. The output from this OR circuit is input to IC511/61 TCACR
SW. The signal that enters this pin determines how much of the MID or
DRC signals will be used for the main picture. When a normal picture is
being shown, then all of the picture will come from the DRC signal. When
PIP is displayed, the main picture will be supplied by DRC and the child
picture will be the MID signal. When features such as Channel Index and
Twin View are used, then the entire picture will be from the MID signal.
The other two inputs are from the Auto Registration’s OSD circuit (BD
board) and IC1004 OSD Processor. The BD board outputs signals to
CN522/6, 7, 8 and 9 which are input to IC511/45, 46, 47 and 48. These
signals are YM/YS and RGB type signals and are used when the cus-
tomer uses the Auto-Focus button on the front panel. They are also used
in the service mode to output the OSD for the PJED section and the dot or
crosshatch patterns used for adjusting. The other signals are output from
IC1004 OSD to four buffers. These buffers are Q1012, Q1002, Q1001
and Q1003. The outputs are taken from their emitters and input to IC511/
49, 50, 51 and 52. These signals are the YM/YS and RGB signals for the
OSD.
Video Outputs
The video signals that are input are combined to form a picture that is
output as R, G and B signals from IC511/35, 37 and 39. These signals
are sent through buffers to CN701, which is connected to the CR board.
They are then sent to their respective C boards where they are amplified
and applied to the cathode of the picture tubes.
IC511/59 VM Out outputs a velocity modulation signal that is applied to
the Z boards for each color. This signal is used to speed up and slow
down the CRT beams as they scan horizontally across the face of the
tubes. This enhances the transitions between light and dark images,
consequently increasing the resolution of the picture.
IK
IK pulses are output along with the video signals from the R, G and B
outputs. These pulses are returned from the C boards and input to IC511/
41 IK In. A window comparator inside IC511 Video Processor monitors
these pulses. This window comparator has a sample and hold circuit for
each color. The sample and hold voltage can be monitored at IC511/36
for red, IC511/38 for green and IC511/40 for blue. If the voltage for any of
these three falls outside of a certain window, the picture will be blanked
and the Timer LED will flash five times as part of the self-diagnostic func-
tion.
Sync Processing
There are separate sync signals output by the MID and DRC circuits that
are input to IC509 Sync Switch. The MID HD signal is input to IC509/15
and the MID VD signal is input to IC509/2. The DRC HD signals are input
to IC509/1 and the DRC VD is input to IC509/12. These signals are
switched by the signal at IC509/9. The VD signal is output at IC509/3 and
input to IC511/65. The HD signal is output from IC509/13 and input to
IC511/66.
These signals are output from IC511 Video Processor as HS Out and VS
Out at pins 29 and 28 respectively. They are sent to IC516 Sync Buffer
before being sent to their respective deflection circuits.
The return signals from the deflection circuits, HBLK and VBLK, are input