STR-DH540
55
Pin No.
Pin Name
I/O
Description
98
RESET
I
Processor Reset. Resets the processor to a known state. Upon deassertion, there is a 4096
CLKIN cycle latency for the PLL to lock. After this time, the core begins program execution
from the hardware reset vector address. The RESET input must be asserted (low) at power-
up.
99
TMS
I
Test Mode Select (JTAG). Used to control the test state machine.
100
VDD_INT
-
Power supply terminal (+1.2V) (for core)
Содержание STR-DH540
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