Sony STR-DH540, Руководство по обслуживанию

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STR-DH540
53
DIGITAL BOARD (4/7) IC2502 ADSST-AVR-3045 (DSP)
Pin No. Pin Name I/O Description
1 VDD_INT - Power supply terminal (+1.2V) (for core)
2 CLK_CFG1 I
Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that the
operating frequency can be changed by programming the PLL multiplier and divider in the
PMCTL register at any time after the core comes out of reset. The allowed values are:
00 = 8:1
01 = 32:1
10 = 16:1
11 = reserved
3 BOOT_CFG0 I Boot Con fi guration Select. These pins select the boot mode for the processor.
4 VDD_EXT - Power supply terminal (+3.3V) (for I/O)
5 VDD_INT - Power supply terminal (+1.2V) (for core)
6 BOOT_CFG1 I Boot Con fi guration Select. These pins select the boot mode for the processor.
7 GND - Ground terminal
8 NC - Not used
9 NC - Not used
10 CLK_CFG0 I
Core to CLKIN Ratio Control. These pins set the start up clock frequency. Note that the
operating frequency can be changed by programming the PLL multiplier and divider in the
PMCTL register at any time after the core comes out of reset. The allowed values are:
00 = 8:1
01 = 32:1
10 = 16:1
11 = reserved
11 VDD_INT - Power supply terminal (+1.2V) (for core)
12 CLKIN I
Local Clock In. Used in conjunction with XTAL. CLKIN is the clock input. It con fi gures the
processors to use either its internal clock generator or an external clock source.
13 XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external crystal.
14 VDD_EXT - Power supply terminal (+3.3V) (for I/O)
15, 16 VDD_INT - Power supply terminal (+1.2V) (for core)
17 RESETOUT/RUNRSTIN I/O
Reset Out/Running Reset In. The default setting on this pin is reset out. This pin also has a
second function as RUNRSTIN which is enabled by setting bit 0 of the RUNRSTCTL register.
For more information, see the ADSP-214xx SHARC Processor Hardware Reference.
18 VDD_INT - Power supply terminal (+1.2V) (for core)
19 MOSI I Serial data input from the main system controller
20 MISO O Serial data output to the main system controller
21 SPICLK I Serial data transfer clock signal input from the main system controller
22 VDD_INT - Power supply terminal (+1.2V) (for core)
23 DPI_P05 I/O
Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU. The
DPI SRU con
fi guration registers de fi ne the combination of on-chip peripheral inputs or
outputs connected to the pin and to the pin’s output enable. The con fi guration registers of
these peripherals then determines the exact behavior of the pin. Any input or output signal
present in the DPI SRU may be routed to any of these pins.
24 DSP_CS I Chip select signal input from the main system controller
25 MD - Not used
26 VDD_EXT - Power supply terminal (+3.3V) (for I/O)
27 DPI_P08 - Not used
28 RESET_MAIN I Reset signal input terminal
29 VDD_INT - Power supply terminal (+1.2V) (for core)
30 UART_OUT O Serial data output terminal
31 UART_IN I Serial data input terminal
32 LED - Not used
33, 34 DPI_P12, DPI_P13 - Not used
35 DAI_P03 - Not used
36 DPI_P14 - Not used
37 to 39 VDD_INT - Power supply terminal (+1.2V) (for core)
40 SL/SR_IN I Audio signal input terminal for SL/SR
41 SL/SR_OUT O Audio signal output to the DSP2 for SL/SR
42 BCLK_IN I Bit clock signal input terminal
43
OPTION_L/
OPTION_R_OUT
- Not used
44 FRONTHI_L/R_OUT - Not used