Sony STR-DH540, Руководство по обслуживанию

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STR-DH540
54
Pin No. Pin Name I/O Description
45 VDD_INT - Power supply terminal (+1.2V) (for core)
46 VDD_EXT - Power supply terminal (+3.3V) (for I/O)
47 VDD_INT - Power supply terminal (+1.2V) (for core)
48 L/R_OUT O Audio signal output to the DSP2 for L/R
49 MID/SW2_OUT O Audio signal output terminal
50 SBL/SBR_OUT O Audio signal output to the DSP2 for SBL/SBR
51 ZONE_L/R - Not used
52 VDD_INT - Power supply terminal (+1.2V) (for core)
53 VDD_EXT - Power supply terminal (+3.3V) (for I/O)
54 MCLK_IN I Master clock signal input from the frequency multiplier
55 VDD_INT - Power supply terminal (+1.2V) (for core)
56 C/SW1_OUT O Audio signal output to the DSP2 for C/SW
57 A/D_2CH I Audio signal input terminal for L/R
58 C/SW_IN I Audio signal input terminal for C/SW
59 LRCLK_IN I L/R sampling clock signal input terminal
60 BCLK_OUT O Bit clock signal output to the DSP2
61 LRCLK_OUT O L/R sampling clock signal output to the DSP2
62 SBL/SBR_IN I Audio signal input terminal for SBL/SBR
63 L/R_IN I Audio signal input terminal for Analog L/R from DIR IC
64 VDD_INT - Power supply terminal (+1.2V) (for core)
65 DIR_IN I Audio signal input terminal
66, 67 VDD_INT - Power supply terminal (+1.2V) (for core)
68 GND - Ground terminal
69 THD_M - Not used
70 THD_P - Not used
71 VDD_THD - Thermal diode power supply
72 to 76 VDD_INT - Power supply terminal (+1.2V) (for core)
77 FLAG0 I/O DSP Interrupt
78, 79 VDD_INT - Power supply terminal (+1.2V) (for core)
80 FLAG1 I/O DSP Error
81 FLAG2 I/O DSP Non Audio
82 FLAG3 - Not used
83 MLBCLK - Not used
84 MLBDAT - Not used
85 MLBDO O
Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB mode. This
serves as the output data pin in 5-pin mode. When the MLB controller is not used, this pin
should be connected to ground.
86 VDD_EXT - Power supply terminal (+3.3V) (for I/O)
87 MLBSIG I/O
Media Local Bus Signal. This is a multiplexed signal which carries the Channel/Address
generated by the MLB Controller, as well as the Command and RxStatus bytes from MLB
devices. In 5-pin mode, this pin is input only. When the MLB controller is not used, this pin
should be grounded.
88 VDD_INT - Power supply terminal (+1.2V) (for core)
89 MLBSO O
Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB mode.
This serves as the output signal pin in 5-pin mode. When the MLB controller is not used, this
pin should be connected to ground.
90 TRST I
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after
power-up or held low for proper operation of the processor.
91 EMU O
Emulation Status. Must be connected to the ADSP-2148x Analog Devices DSP Tools product
line of JTAG emulators target board connector only.
92 TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path.
93 VDD_EXT - Power supply terminal (+3.3V) (for I/O)
94 VDD_INT - Power supply terminal (+1.2V) (for core)
95 TDI I Test Data Input (JTAG). Provides serial data for the boundary scan logic.
96 TCK I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted (pulsed
low) after power-up or held low for proper operation of the device.
97 VDD_INT - Power supply terminal (+1.2V) (for core)