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BASE I-TAD BOARD U1 PCD6002-C (TAD)
Pin No.
Pin Name
I/O
Description
1
PSEN
O
Not used (open)
2
EAN
I
Not used (fixed at “L”)
3
VPP
—
Not used (open)
4
7SEG D1
O
LED drive signal output of the 7 Segments LED (U1) “L”: LED on
5
7SEG D2
O
LED drive signal output of the 7 Segments LED (U1) “L”: LED on
6
LED SEL
O
B+ switch (for LEDs) (Q10) control signal output “L”: B+ switch on
7
RESERVED
O
Not used
8
RESET
O
Reset signal output to the EEPROM (U3) “H”: reset
9
L LATCH
O
Serial data latch pulse output to the 7 segments LED drive (U10)
10
L CLK
O
Serial data transfer clock signal output to the 7 segments LED drive (U10)
11
L DATA
O
Serial data output to the 7 segments LED drive (U10)
12
VDD3V2
—
Power supply terminal (+3V) (digital system)
13
VSS3V1
—
Ground terminal
14 to 18 ROW0 to ROW4
O
Key send signal output to the key matrix
19
ROW5
O
Key send signal output to the key matrix Not used
20
HOOK SW
O
Hook on/off control signal output terminal “L”: off hook, “H”: on hook
21
NINT
I/O
Not used
22
VSS3V3
—
Ground terminal
23
SPK+
O
Analog audio signal (+) output to the speaker (SP1)
24
SPK–
O
Analog audio signal (–) output terminal Not used (open)
25
MIC+
I
Analog audio signal (+) input from the microphone (MIC1)
26
MIC–
I
Analog audio signal (–) input from the microphone (MIC1)
27
VMIC
O
Reference voltage output terminal (+2V)
28
VSSA
—
Ground terminal
29
VBGP
O
Band gap voltage output terminal (+1.2V) Not used
30
VMIC
O
Reference voltage output terminal (+2V)
31
AD0IN
I
Line DC input terminal
32
AD1IN
I
Analog input to the internal A/D converter Not used (pull up)
33
DAOUT
O
Analog output from the internal D/A converter Not used (open)
34
VDDA
—
Power supply terminal (+3V) (analog system)
35
LIFPIN
I
Analog audio signal input terminal Not used
36
LIFMIN2
I
Analog audio signal input from the TEL line
37
LIFMIN1
I
Analog audio signal input from the greeting recorder (U4)
38
LIFMOUT
O
Analog audio signal output terminal Not used (open)
39
LIFMOUT/DTMF
O
Analog audio/DTMF signal output to the TEL line
40
VSSPLL
—
Ground terminal
41
XTAL2
O
System clock output terminal (3.579545MHz)
42
XTAL1
I
System clock input terminal (3.579545MHz)
43
VDDPLL
—
Power supply terminal (+3V) (system clock and PLL circuit)
44
VDD3V3
—
Power supply terminal (+3V) (digital system)
45
RINGER DET
I
Detect signal input of the ringer coming “L”: ringer is detected
46
MOUT1/DCK
I/O
Not used (open)
47
CTR ACTIVE
I
Not used
48
S CLOCK/PARA DET
I/O
Not used
49
T0
I/O
Not used (open)
50
BU HOOK
I
Hook on/off detect signal input terminal “L”: off hook, “H”: on hook
Содержание SPP-A941 - Cordless Telephone With Answering System
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Страница 21: ...SPP A941 25 26 5 6 SCHEMATIC DIAGRAM BASE RF Board See page 43 for IC Block Diagrams Page 30 ...
Страница 25: ...SPP A941 33 34 5 10 SCHEMATIC DIAGRAM BASE I TAD Board See page 31 for Waveform Page 30 Page 30 ...
Страница 28: ...SPP A941 39 40 5 14 SCHEMATIC DIAGRAM HAND RF Board See page 43 for IC Block Diagrams Page 42 ...